Datasheet
Table Of Contents
- General Description
- Key Features
- Applications
- System Diagrams
- Contents
- Figures
- Tables
- Legal
- Product Family
- 1 Terms and Definitions
- 2 Block Diagram
- 3 Pinout
- 4 Characteristics
- 5 Functional Description
- 5.1 Features Description
- Driving LRA and ERM Actuators
- Automatic LRA Resonant Frequency Tracking
- Wideband LRA Support
- I2C and PWM Input Streaming
- Low Latency I2C/GPI Wake-Up from IDLE State
- Three GPI Sequence Triggers for up to Six Independent Haptic Responses
- On-Board Waveform Memory with Amplitude, Time, and Frequency Control
- Active Acceleration and Rapid Stop for High-Fidelity Haptic Feedback
- Continuous Actuator Diagnostics and Fault Handling
- No Software Requirements with Embedded Operation
- Differential Output Drive
- Current Driven System
- Configurable EMI Suppression
- Automatic Short Circuit Protection
- Ultra-Low Power Consumption with State Retention
- Ultra-Low Latency in STANDBY State
- Supply Monitoring, Reporting, and Automatic Output Limiting
- Open- and Closed-Loop Modes
- Open-Loop Sine/Custom Wave Drive Support
- Small Solution Footprint
- Additional Features
- 5.2 Functional Modes
- 5.3 Resonant Frequency Tracking
- 5.4 Active Acceleration and Rapid Stop
- 5.5 Wideband Frequency Control
- 5.6 Device Configuration and Playback
- 5.7 Advanced Operation
- 5.7.1 Frequency Tracking
- 5.7.2 Rapid Stop
- 5.7.3 Initial Impedance Update
- 5.7.4 Amplitude PID
- 5.7.5 Wideband Operation
- 5.7.6 Custom Waveform Operation
- 5.7.7 Embedded Operation
- 5.7.8 Polarity Change Reporting for Half-Period Control in DRO Mode
- 5.7.9 Loop Filter Configuration
- 5.7.10 UVLO Threshold
- 5.7.11 Edge Rate Control
- 5.7.12 Double Output Current Range
- 5.7.13 Supply Monitoring, Reporting, and Automatic Output Limiting
- 5.7.14 BEMF Fault Limit
- 5.7.15 Increasing Impedance Detection Accuracy
- 5.7.16 Frequency Pause during Rapid Stop
- 5.7.17 Frequency Pause during Rapid Stop
- 5.7.18 Coin ERM Operation
- 5.8 Waveform Memory
- 5.9 General Data Format
- 5.10 I2C Control Interface
- 5.1 Features Description
- 6 Register Overview
- 7 Package Information
- 8 Ordering Information
- 9 Application Information
- 10 Layout Guidelines
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
Datasheet
Revision 3.0
30-Jul-2019
CFR0011-120-00
12 of 76
© 2019 Dialog Semiconductor
4.4 Timing Characteristics
Unless otherwise noted, the parameters listed in Table 8 are valid for T
A
= 25 ºC, V
DD
= 3.8 V, and
V
DDIO
= 1.8 V.
Table 8: Timing Characteristics
Parameter
Description
Conditions
Min
Typ
Max
Unit
t
ON
Cold boot to IDLE state time
V
DD
present and PoR released
1.2
1.5
ms
t
OUT_IDLE
Time to output from IDLE
state
From GPI or I
2
C trigger to output
drive
0.75
ms
t
OUT_STANDBY
Time to output from
STANDBY state
From GPI or I
2
C trigger to output
drive
0.15
ms
STOP
SDA
SCL
t
FALL
t
RISE
t
FALL
START
t
HOLD_START
t
HOLD_DATA
1/f
SCL
70%
30%
70%
30%
t
SETUP_DATA
t
LO_SCL
t
HI_SCL
t
DATA
ACK
t
DATA_ACK
t
SETUP_STOP
t
SETUP_START
Figure 4: I
2
C Interface Timing
Table 9: I
2
C Interface Timing Requirements
Parameter
Description
Conditions
Min
Max
Unit
t
BUF
Bus free time from STOP to START condition
0.5
µs
Standard, Fast, and Fast-Plus Modes
C
BUS
Bus line capacitive load
520
pF
f
SCL
SCL clock frequency
0
1000
(Note 1)
kHz
t
SETUP_START
Start condition setup time
0.26
µs
t
HOLD_START
Start condition hold time
0.26
µs
t
LO_SCL
SCL low time
0.5
µs
t
HI_SCL
SCL high time
0.26
µs
t
RISE
SCL and SDA rise time
120
ns
t
FALL
SCL and SDA fall time
120
ns
t
SETUP_DATA
Data setup time
50
ns
t
HOLD_DATA
Data hold-time
0
ns
t
SETUP_STOP
Stop condition setup time
0.26
µs
t
DATA
Data valid time
0.45
µs
t
DATA_ACK
Data valid acknowledge time
0.45
µs
t
SPIKE
Spike suppression (SCL, SDA)
Fast/Fast+ mode
50
ns
Note 1 f
SCL
maximum is 400 kHz at V
DDIO
≤ 1.65 V and 1000 kHz at V
DDIO
> 1.65 V.