Product Specifications

CY8C29466/CY8C29566
CY8C29666/CY8C29866
Document Number: 38-12013 Rev. AB Page 61 of 67
Errata
This section describes the errata for the PSoC Programmable System-on-Chip, CY8C29xxx family of devices. Details include errata
trigger conditions, scope of impact, available workaround, and silicon revision applicability. Contact your local Cypress Sales
Representative if you have questions.
Qualification Status
Product Status: In Production
Errata Summary
The following table defines the errata applicability to available CY8C29xxx family devices.
1. Invalid Flash reads may occur if VDD is pulled to –0.5 V just before power-on
■ Problem Definition
When V
DD
of the device is pulled below ground just before power-on; the first read from each 8 K Flash bank may be corrupted.
This issue does not affect Flash bank 0 because it is the selected bank upon reset.
■ Parameters Affected
When VDD is pulled below ground prior to power-on, an internal Flash reference may deviate from its nominal voltage. The
reference deviation tends to result in the first Flash read from that bank returning 0xFF. During the first read from each bank, the
reference is reset resulting in all future reads returning the correct value. A short delay of 5 µs before the first real read provides
time for the reference voltage to stabilize. When V
DD
of the device is pulled below ground just before power-on; the first read from
each 8K Flash bank may be corrupted apart from Flash bank 0. This can be solved by doing a dummy read from each Flash bank
prior to use of the Flash banks.
■ Workaround
To prevent an invalid Flash read, a dummy read from each Flash bank must occur prior to use of the Flash banks. A delay of 5 µs
must occur after the dummy read and before a real read. The dummy reads should occur as soon as possible and must be located
in Flash bank 0 prior to a read from any other Flash bank. An example for reading a byte of memory from each Flash bank is listed
below and should be placed in boot.tpl and boot.asm immediately after the ‘start:’ label.
Part Numbers Affected
Part Number Ordering Information
CY8C29xxx CY8C29466-24PXI
CY8C29466-24PVXI
CY8C29466-24PVXIT
CY8C29466-24SXI
CY8C29466-24SXIT
CY8C29566-24AXI
CY8C29566-24AXIT
CY8C29666-24PVXI
CY8C29666-24PVXIT
CY8C29666-24LFXI
CY8C29866-24AXI
CY8C29000-24AXI
Items Part Number Silicon Revision Fix Status
[1]. Invalid Flash reads may occur if VDD is pulled to –0.5 V just
before power-on
CY8C29xxx A No silicon fix is planned.
Workaround is required.
[2]. Internal main oscillator (IMO) tolerance deviation at
temperature extremes
CY8C29xxx A No silicon fix planned.
Workaround is required.