Product Specifications

CY8C29466/CY8C29566
CY8C29666/CY8C29866
Document Number: 38-12013 Rev. AB Page 51 of 67
Thermal Impedances Capacitance on Crystal Pins
Solder Reflow Specifications
Tab le 43 shows the solder reflow temperature limits that must not be exceeded.
Table 41. Thermal Impedances per Package
Package Typical 
JA
[
30]
28-pin PDIP 69 °C/W
28-pin SSOP 94 °C/W
28-pin SOIC 67 °C/W
44-pin TQFP 60 °C/W
48-pin SSOP 69 °C/W
48-pin QFN
[31]
28 °C/W
100-pin TQFP 50 °C/W
Notes
30. T
J
= T
A
+ POWER × 
JA.
31. To achieve the thermal impedance specified for the QFN package, refer to the application note Design Guidelines for Cypress Quad Flat No Extended Lead
(QFN) Packaged Devices – AN72845
available at http://www.cypress.com.
Table 42. Typical Package Capacitance on Crystal Pins
Package Package Capacitance
28-pin PDIP 3.5 pF
28-pin SSOP 2.8 pF
28-pin SOIC 2.7 pF
44-pin TQFP 2.6 pF
48-pin SSOP 3.3 pF
48-pin QFN 1.8 pF
100-pin TQFP 3.1 pF
Table 43. Solder Reflow Specifications
Package
Maximum Peak Temperature
(T
C
)
Maximum Time above
T
C
– 5 °C
28-pin PDIP
260 °C 30 seconds
28-pin SSOP
260 °C 30 seconds
28-pin SOIC
260 °C 30 seconds
44-pin TQFP
260 °C 30 seconds
48-pin SSOP
260 °C 30 seconds
48-pin QFN
260 °C 30 seconds
100-pin TQFP
260 °C 30 seconds