Product Specifications

CY8C29466/CY8C29566
CY8C29666/CY8C29866
Document Number: 38-12013 Rev. AB Page 47 of 67
Packaging Information
This section illustrates the packaging specifications for the CY8C29x66 PSoC device, along with the thermal impedances for each
package and the typical package capacitance on crystal pins.
Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of
the emulation tools' dimensions, refer to the emulator pod drawings at http://www.cypress.com.
Packaging Dimensions
Figure 20. 28-pin PDIP (300 Mils) Package Outline, 51-85014
51-85014 *G