Product Specifications
CY8C29466/CY8C29566
CY8C29666/CY8C29866
Document Number: 38-12013 Rev. AB Page 11 of 67
44-Pin Part Pinout
Table 3. 44-Pin Part Pinout (TQFP)
Pin
No.
Type
Pin
Name
Description
Figure 5. CY8C29566 44-Pin PSoC Device
Digital Analog
1 I/O P2[5]
2 I/O I P2[3] Direct switched capacitor block input
3 I/O I P2[1] Direct switched capacitor block input
4 I/O P4[7]
5 I/O P4[5]
6 I/O P4[3]
7 I/O P4[1]
8 Power SMP Switch mode pump (SMP) connection to
external components required
9 I/O P3[7]
10 I/O P3[5]
11 I/O P3[3]
12 I/O P3[1]
13 I/O P1[7] I
2
C SCL
14 I/O P1[5] I
2
C SDA
15 I/O P1[3]
16 I/O P1[1] Crystal (XTALin), I
2
C SCL, ISSP-SCLK
[6]
17 Power V
SS
Ground connection
18 I/O P1[0] Crystal (XTALout), I
2
C SDA, ISSP-SDATA
[6]
19 I/O P1[2]
20 I/O P1[4] Optional EXTCLK
21 I/O P1[6]
22 I/O P3[0]
23 I/O P3[2]
24 I/O P3[4]
25 I/O P3[6]
26 Input XRES Active high external reset with internal
pull-down
27 I/O P4[0]
28 I/O P4[2]
29 I/O P4[4]
30 I/O P4[6]
31 I/O I P2[0] Direct switched capacitor block input
32 I/O I P2[2] Direct switched capacitor block input
33 I/O P2[4] External analog ground (AGND)
34 I/O P2[6] External voltage reference (VREF)
35 I/O I P0[0] Analog column mux input
36 I/O I/O P0[2] Analog column mux input and column output
37 I/O I/O P0[4] Analog column mux input and column output
38 I/O I P0[6] Analog column mux input
39 Power V
DD
Supply voltage
40 I/O I P0[7] Analog column mux input
41 I/O I/O P0[5] Analog column mux input and column output
42 I/O I/O P0[3] Analog column mux input and column output
43 I/O I P0[1] Analog column mux input
44 I/O P2[7]
LEGEND: A = Analog, I = Input, and O = Output.
TQFP
P3[1]
P2[7]
P2[5] P2[4], External AGND
A, I, P2[3] P2[2], A, I
A, I, P2[1] P2[0], A, I
P4[7]
P4[6]
P4[5]
P4[4]
P4[3]
P4[2]
P4[1]
P4[0]
SMP XRES
P3[7]
P3[6]
P3[5] P3[4]
P3[3] P3[2]
I2C SCL, P1[7]
P0[1], A, I
I2C SDA, P1[5]
P0[3], A, IO
P1[3]
P0[5], A, IO
I2C SCL, XTALin, P1[1]
P0[7], A, I
V
SS
V
DD
I2C SDA, XTALout, P1[0]
P0[6], A, I
P1[2]
P0[4], A, IO
EXTCLK, P1[4]
P0[2], A, IO
P1[6]
P0[0], A, I
P3[0]
P2[6], External VREF
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
44
43
42
41
40
39
38
37
36
35
34
13
14
15
16
17
18
19
20
21
22
12
Note
6. These are the ISSP pins, which are not High Z at POR. See the PSoC Programmable System-on-Chip Technical Reference Manual for details.