Data Sheet

PRELIMINARY
VS1063a Datasheet
9 FUNCTIONAL DESCRIPTION
9.8 SCI Registers
VS1063a sets DREQ low when it detects an SCI operation (this delay is 16 to 40 CLKI cycles
depending on whether an interrupt service routine is active) and restores it when it has pro-
cessed the operation. The duration depends on the operation. If DREQ is low when an SCI
operation is performed, it also stays low after SCI operation processing.
If DREQ is high before an SCI operation, do not start a new SCI/SDI operation before DREQ is
high again. If DREQ is low before a SCI operation because the SDI can not accept more data,
make certain there is enough time to complete the operation before sending another.
SCI registers, prefix SCI_
Reg Typ. Reset Write Time
1
Name Description
0x0 rw 0x4000
6
80 CLKI
4
MODE Mode control
0x1 rw 0x000C
3
80 CLKI STATUS Status of VS1063a
0x2 rw 0 80 CLKI BASS Built-in bass/treble control
0x3 rw 0 1200 XTALI
5
CLOCKF Clock freq + multiplier
0x4 rw 0 100 CLKI DECODE_TIME Decode time in seconds
0x5 rw 0 450 CLKI
2
AUDATA Misc. audio data
0x6 rw 0 100 CLKI WRAM RAM write/read
0x7 rw 0 100 CLKI WRAMADDR Set address for RAM write/read
0x8 r 0 80 CLKI HDAT0 Stream header data 0
0x9 r 0 80 CLKI HDAT1 Stream header data 1
0xA rw 0 210 CLKI
2
AIADDR Start address of application/plugin
0xB rw 0 80 CLKI VOL Volume control
0xC rw 0 80 CLKI
2
AICTRL0 Application control register 0
0xD rw 0 80 CLKI
2
AICTRL1 Application control register 1
0xE rw 0 80 CLKI
2
AICTRL2 Application control register 2
0xF rw 0 80 CLKI
2
AICTRL3 Application control register 3
1
This is the worst-case time that DREQ stays low after writing to this register. The user may
choose to skip the DREQ check for those register writes that take less than 100 clock cycles to
execute and use a fixed delay instead.
2
In addition, the cycles spent in the user application/plugin routine must be counted.
3
Firmware changes the value of this register immediately to 0x68 (analog enabled), and after
a short while to 0x60 (analog drivers enabled).
4
When mode register write specifies a software reset the worst-case time is 22000 XTALI
cycles.
5
If the clock multiplier is changed, writing to SCI_CLOCKF register may force internal clock
to run at 1.0 × XTALI for a while. Thus it is not a good idea to send SCI or SDI bits while this
register update is in progress.
6
Firmware changes the value of this register immediately to 0x4800.
Reads from all SCI registers complete in under 100 CLKI cycles, except for SCI_AIADDR,
which may take 200 cycles. In addition the cycles spent in the user application/plugin routine
must be counted to the read time of SCI_AIADDR, SCI_AUDATA, and SCI_AICTRL0. . . 3.
Some bits in SCI_MODE and SCI_STATUS are hardware bits; other registers only control the
firmware. See VS1063 Hardware Guide for details.
Version: 0.42, 2011-11-24 39