Data Sheet

PRELIMINARY
VS1063a Datasheet
9 FUNCTIONAL DESCRIPTION
After that the data is fed to the Audio FIFO. The size of the audio FIFO is 2048 stereo (2×16-bit)
samples, or 8 KiB.
Now decoded and processed audio is sent to a samplerate converter, where volume control is
applied. After this step it is combined with an optional sidestream which may be either PCM
samples coming through the SCI bus or analog data from the line/mic input.
The samplerate converter upsamples all different samplerates to XTALI/2, or 128 times the
highest usable samplerate with 18-bit precision. Volume control is performed in the upsampled
domain. New volume settings are loaded only when the upsampled signal crosses the zero
point (or after a timeout). This zero-crossing detection almost completely removes all audible
noise that occurs when volume is suddenly changed.
The samplerate conversion to a common samplerate removes the need for complex PLL-based
clocking schemes and allows almost unlimited samplerate accuracy with one fixed input clock
frequency. With a 12.288 MHz clock, the DA converter operates at 128 × 48 kHz, i.e. 6.144
MHz, and creates a stereo in-phase analog signal. The oversampled output is low-pass filtered
by an on-chip analog filter. This signal is then forwarded to the earphone amplifier.
9.3 Encoder Data Flow of VS1063a
To UART
Bitstream
out FIFO
UartTxEna=1
To SCI
UartTxEna=0
Mic/Line In
FIFO
Audio in
decimator
Software
SRC
ADC
Encoder
WAV
MP3,OGG,
Resampler
SCI_VOL
DAC
SRC
To DAC
Figure 14: Encoder data flow of VS1063a
Figure 14 presents the encoder dataflow of VS1063a.
Depending on which samplerate the user has requested, data is read from the Analog-to-Digital
Converter with one of samplerates or 12, 24, or 48 kHz. A 10 Hz subsonic high-pass filter (not
shown in the figure) is applied to the signal.
Here audio is split into two: one path going to monitoring, the other path going to the encoder.
Depending whether the signal needs to be resampled, it may be fed to the Resampler Sample
Rate Converter that is used for samplerate fine tuning, and/or to the Software decimator which
can decimate the signal by 2 or 3. (E.g. if chosen samplerate is 8 kHz, it will be digitized at
24 kHz, then downsampled by 3 with the Software decimator).
From the decimator stages, audio is fed to audio in FIFO, from which the encoder reads the
samples.
The bitstream generated by the encoder is fed to the Bitstream out FIFO. The data is then either
read through SCI by the user or output by the VS1063a to the UART.
Version: 0.42, 2011-11-24 35