Data Sheet

PRELIMINARY
VS1063a Datasheet
7 SPI BUSES
7.4 Serial Protocol for Serial Data Interface (SDI)
7.4.1 General
The serial data interface operates in slave mode so DCLK signal must be generated by an
external circuit.
Data (SDATA signal) can be clocked in at either the rising or falling edge of DCLK (Chapter 9.8).
VS1063a assumes its data input to be byte-sychronized. SDI bytes may be transmitted either
MSb or LSb first, depending of register SCI_MODE bit SM_SDIORD (Chapter 9.8.1).
The firmware is able to accept the maximum bitrate the SDI supports.
7.4.2 SDI in VS10xx Native Modes (New Mode)
In VS10xx native modes (SM_NEWMODE is 1), byte synchronization is achieved by XDCS.
The state of XDCS may not change while a data byte transfer is in progress. To always main-
tain data synchronization even if there may be glitches in the boards using VS1063a, it is
recommended to turn XDCS every now and then, for instance once after every disk data block,
just to make sure the host and VS1063a are in sync.
If SM_SDISHARE is 1, the XDCS signal is internally generated by inverting the XCS input.
For new designs, using VS10xx native modes are recommended.
Version: 0.42, 2011-11-24 19