Datasheet-2

a-Si TFT LCD Single Chip Driver
132RGBx162 Resolution and 262K color
ILI9163C
Page 66 of 200 Version:0.09
9. Power ON/OFF Sequence
VDDI and VCI can be applied in any order.
VCI and VDDI can be powered down in any order.
During power off, if LCD is in the Sleep Out mode, VCI and VDDI must be powered down minimum
120msec after RESX has been released.
During power off, if LCD is in the Sleep In mode, VDDI or VCI can be powered down minimum 0msec after
RESX has been released.
CSX can be applied at any timing or can be permanently grounded. RESX has priority over CSX.
Notes:
1. There will be no damage to the display module if the power sequences are not met.
2. There will be no abnormal visible effects on the display panel during the Power On/Off Sequences.
3. There will be no abnormal visible effects on the display between end of Power On Sequence and before
receiving Sleep Out command. Also between receiving Sleep In command and Power Off Sequence.
4. If RESX line is not held stable by host during Power On Sequence as defined in Sections 9.1 and 9.2, then it
will be necessary to apply a Hardware Reset (RESX) after Host Power On Sequence is complete to ensure
correct operation. Otherwise function is not guaranteed.
9.1 Case 1 – RESX line is held high or Unstable by Host at Power –On
If RESX line is held high or unstable by the host during Power On, then a Hardware Reset must be applied after
both VCI and VDDI have been applied – otherwise correct functionality is not guaranteed. There is no timing
restriction upon this hardware reset.
Note: Unless otherwise specified, timings herein show cross point at 50% of signal/power level.
9.2 Case 2 – RESX line is held Low by Host at Power On
If RESX line is held Low (and stable) by the host during Power On, then the RESX must be held low for minimum