Datasheet-2

a-Si TFT LCD Single Chip Driver
132RGBx162 Resolution and 262K color
ILI9163C
Page 38 of 200 Version:0.09
The timing chart of 6-bit RGB interface mode is shown as below:
HS
VS
PCLK
EN
D[17:12]
Back porch
VLW>=1H
1 frame
Front porch
Valid data
HLW>=3DOTCLKs
1H
DTST>=HLW
HS
PCLK
EN
D[17:12]
VLW : VS Low Width
HLW : HS Low Width
DTST : Data Transfer Startup Time
RG BRG B B RG B
Note 1: In 6-bit RGB interface mode, each dot of one pixel (R, G and B) is transferred in synchronization with
PCLK.
Note 2: In 6-bit RGB interface mode, set the cycles of VS, HS and EN to 3 multiples of PCLK.
Figure25: Timing Chart of Signals in 6-bit RGB Interface Mode