Datasheet-2

a-Si TFT LCD Single Chip Driver
132RGBx162 Resolution and 262K color
ILI9163C
Page 35 of 200 Version:0.09
6.8 RGB Interface
6.8.1 RGB Interface Selection
The RGB interface mode is available for ILI9163C and the interface is selected by setting the VIPF[3:0] bits as
following table.
VIPF[3:0] RGB Interface Data Bus
0 1 1 0 18-bit RGB interface D[17:0]
0 1 0 1 16-bit RGB interface D[17:13], D[11:1]
1 1 1 0 6-bitRGB interface D[7:2]
Others Setting prohibited
The display operation via RGB interface is synchronized with the VS, HS and PCLK signals. The RGB interface
transfers the updated data to GRAM and the update area is defined by the window address function. The back
porch and back porch are used to set the RGB interface timing.

Parallel RGB Interface Set Table
18-bit data bus interface (D[17:0] is used) , VIPF[3:0] = 0110
D17 D16 D15 D14 D13 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1D11
R[4] R[3] R[2] R[1] R[0] G[5 ] G[4] G[3 ] G[2] G[ 1] G[0] B[4] B[ 3 ] B[2 ] B[ 1 ] B[ 0 ]16bpp Frame Memory Write
16-bit data bus interface (D[17:13] and D[11:1] are used) , VIPF[3:0] = 0101
R[5] R[4] R[3] R[2] R[1] R[0] G[5] G[4 ] G[3] G[ 2] G[1] G[ 0] B[ 5 ] B[4 ] B[ 3 ] B[2 ] B[1] B[0]18bpp Frame Memory Write
6-bit data bus interface (D[7:2] is used) , VIPF[3] = 1110
D7 D6 D5 D4 D3 D2
First Tran sf er Secon d Transfer
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
R[5] R[4] R[3] R[2] R[1] R[0] G[5] G[4 ] G[3] G[ 2] G[1] G[ 0] B[ 5 ] B[4 ] B[ 3 ] B[2 ] B[1] B[0]18bpp Frame Memory Write
D7 D6 D5 D4 D3 D2 D7 D6 D5 D4 D3 D2
Third Transfer
Pixel clock (PCLK) is running all the time without stopping and it is used to entering VS, HS, EN and D[17:0] states
when there is a rising edge of the PCLK. The PCLK can not be used as continues internal clock for other functions
of the display module.
Vertical synchronization (VS) is used to tell when there is received a new frame of the display. This is high enable
and its state is read to the display module by a rising edge of the PCLK signal.
Horizontal synchronization (HS) is used to tell when there is received a new line of the frame. This is low enable
and its state is read to the display module by a rising edge of the PCLK signal.