Datasheet-2

a-Si TFT LCD Single Chip Driver
132RGBx162 Resolution and 262K color
ILI9163C
Page 29 of 200 Version:0.09
6.4.1 Write Cycle/Sequence
The write cycle means that the host writes information (command or/and data) to the display via the interface.
Each write cycle (E low-high-low sequence) consists of 3 control (D/CX, E, R/WX) and data signals (D[17…0]).
D/CX bit is a control signal, which tells if the data is a command or a data. The data signals are a command if the
control signal is low (= ‘0’) and vice versa it is data (= ‘1’). The write cycle is described in the following figure.
E
D[7:0], D[8:0] or
D[15:0], D[17:0]
The host asserts D[17:0],
D[15:0], D[8:0] or D[7:0] lines
when there is falling edge of
E
The display read D[17:0],
D[15:0], D[8:0] or D[7:0]
lines when there is rising
edge of E
The host negates D[17:0],
D[15:0], D[8:0] or D[7:0]
lines.
R/WX = 0
Note: E is unsynchronized signal (it can be stopped)
Figure13: 6800-Series Write Protocol
S
CMD CMD PA 1 CMD
PA N-2
P
PA 1
CSX
D/CX
E
1-byte command
2-byte command
N-byte command (number of parameter = N-1
Signals on D[17:0], D/CX, R/WX, E pins
during CSX= 1 are ignore
CMD: Write command code
PA: Write parameter or RAM data
PA N-1
D[17:0]
RESX
1
R/WX
S
CMD CMD PA 1 CMD
PA N-2
P
PA 1
PA N-1
D[17:0]
S
CMD CMD PA 1 CMD
PA N-2
P
PA 1
PA N-1
Host [17:0]
Host to LCD
Driver [17:0]
LCD to Host
Figure14: 6800-Series parallel bus protocol (write to register or display RAM)