User Manual

MPU-9250 Register Map and Descriptions
Document Number: RM-MPU-9250A-00
Revision: 1.4
Release Date: 9/9/2013
BIT
NAME
FUNCTION
[7:0]
I2C_SLV4_DI[7:0]
Data read from I2C Slave 4.
4.18 Register 54 – I
2
C Master Status
Serial IF: R/C
Reset value: 0x00
BIT
NAME
FUNCTION
[7]
PASS_THROUGH
Status of FSYNC interrupt – used as a way to pass an external interrupt
through this chip to the host. If enabled in the INT_PIN_CFG register by
asserting bit FSYNC_INT_EN and if the FSYNC signal transitions from low to
high, this will cause an interrupt. A read of this register clears all status bits
in this register.
[6]
I2C_SLV4_DONE
Asserted when I2C slave 4’s transfer is complete, will cause an interrupt if bit
I2C_MST_INT_EN in the INT_ENABLE register is asserted, and if the
SLV4_DONE_INT_EN bit is asserted in the I2C_SLV4_CTRL register.
[5]
I2C_LOST_ARB
Asserted when I2C slave looses arbitration of the I2C bus, will cause an
interrupt if bit I2C_MST_INT_EN in the INT_ENABLE register is asserted.
[4]
I2C_SLV4_NACK
Asserted when slave 4 receives a nack, will cause an interrupt if bit
I2C_MST_INT_EN in the INT_ENABLE register is asserted.
[3]
I2C_SLV3_NACK
Asserted when slave 3 receives a nack, will cause an interrupt if bit
I2C_MST_INT_EN in the INT_ENABLE register is asserted.
[2]
I2C_SLV2_NACK
Asserted when slave 2 receives a nack, will cause an interrupt if bit
I2C_MST_INT_EN in the INT_ENABLE register is asserted.
[1]
I2C_SLV1_NACK
Asserted when slave 1 receives a nack, will cause an interrupt if bit
I2C_MST_INT_EN in the INT_ENABLE register is asserted.
[0]
I2C_SLV0_NACK
Asserted when slave 0 receives a nack, will cause an interrupt if bit
I2C_MST_INT_EN in the INT_ENABLE register is asserted.
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