User Manual

MPU-9250 Register Map and Descriptions
Document Number: RM-MPU-9250A-00
Revision: 1.4
Release Date: 9/9/2013
BIT
NAME
FUNCTION
[3:0]
I2C_MST_CLK [3:0]
I2C_MST_CLK is a 4 bit unsigned value which configures a divider on the MPU-
9250 internal 8MHz clock. It sets the I
2
C master clock speed according to the
following table:
I2C_MST_CLK
I
2
C Master Clock
Speed
8MHz Clock
Divider
0
348 kHz
23
1
333 kHz
24
2 320 kHz 25
3
308 kHz
26
4
296 kHz
27
5 286 kHz 28
6
276 kHz
29
7
267 kHz
30
8 258 kHz 31
9
500 kHz
16
10
471 kHz
17
11
444 kHz
18
12 421 kHz 19
13
400 kHz
20
14
381 kHz
21
15 364 kHz 22
Note: For further information regarding the association of EXT_SENS_DATA registers to particular
slave devices, please refer to Registers 73 to 96.
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