User Manual

MPU-9250 Register Map and Descriptions
Document Number: RM-MPU-9250A-00
Revision: 1.4
Release Date: 9/9/2013
0 3.91 1.1 k 1
0 7.81 1.1 k 1
0 15.63 1.1 k 1
0 31.25 1.1 k 1
0 62.50 1.1 k 1
0 125 1.1 k 1
0 250 1.1 k 1
0 500 1.1 kHz 1
As you can see from the tables above, some of the ODRs can be configured in the normal
accelerometer mode as well as low power mode.
For further details on how to configure the individual ODRs, please refer to register 30 Low Power
Accelerometer ODR Control.
4.9 Register 30 – Low Power Accelerometer ODR Control
Serial IF: R/W
Reset value: 0x00
BIT
NAME
FUNCTION
[7:4]
Reserved
[3:0]
lposc_clksel[3:0]
Sets the frequency of waking up the chip to take a sample of accel
data – the low power accel Output Data Rate.
Lposc_clksel
Output Frequency (Hz)
0
0.24
1 0.49
2
0.98
3
1.95
4 3.91
5
7.81
6
15.63
7
31.25
8
62.50
9
125
10
250
11 500
12-15
RESERVED
16 of 55