User Manual

MPU-9250 Register Map and Descriptions
Document Number: RM-MPU-9250A-00
Revision: 1.4
Release Date: 9/9/2013
BIT
NAME
FUNCTION
[7:6]
Reserved
[5:4]
Reserved
[3]
accel_fchoice_b
Used to bypass DLPF as shown in table 2 below. NOTE: This register
contains accel_fchoice_b (the inverted version of accel_fchoice as
described in the table below).
[2:0]
A_DLPFCFG
Accelerometer low pass filter setting as shown in table 2 below.
Accelerometer Data Rates and Bandwidths (Normal Mode)
ACCEL_FCHOICE A_DLPF_CFG
Output
Bandwidth
(Hz)
Delay
(ms)
Noise
Density
(ug/rtHz)
Rate
(kHz)
0
X
1.13 K
0.75
250 4
1
0
460
1.94
250 1
1
1
184
5.80
250 1
1
2
92
7.80
250 1
1
3
41
11.80
250 1
1
4
20
19.80
250 1
1
5
10
35.70
250 1
1
6
5
66.96
250
1
1
7
460
1.94
250
1
The data output rate of the DLPF filter block can be further reduced by a factor of 1/(1+SMPLRT_DIV),
where SMPLRT_DIV is an 8-bit integer. Following is a small subset of ODRs that are configurable for the
accelerometer in the normal mode in this manner (Hz):
3.91, 7.81, 15.63, 31.25, 62.50, 125, 250, 500, 1K
The following table lists the approximate accelerometer filter bandwidths available in the low-power mode of
operation.
In the low-power mode of operation, the accelerometer is duty-cycled. Fchoice=0 for all options.
Accelerometer Data Rates and Bandwidths (Low-Power Mode)
ACCEL_FCHOICE
ODR
(Hz)
Output
Bandwidth
(Hz)
Delay
(ms)
0 0.24 1.1 k 1
0 0.49 1.1 k 1
0 0.98 1.1 k 1
0 1.95 1.1 k 1
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