Manual

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ZED-F9T-Integration manual
Figure 42: RF input trace
The RF_IN trace on the top layer should be referenced to a suitable ground layer.
4.7.4.2 Vias for the ground pads
The ground pads under the ZED-F9T high accuracy timing receiver need to be grounded with vias to
the lower ground layer of the PCB. A solid ground layer fill on the top layer of the PCB is recommended.
This is shown in the figure below.
Figure 43: Top layer fill and vias
4.7.4.3 VCC pads
The VCC pads for the ZED-F9T high accuracy timing receiver must have as low impedance as
possible with large vias to the lower power layer of the PCB. The VCC pads need a large combined
pad and the de-coupling capacitors must be placed as close as possible. This is shown in the figure
below.
UBX-19005590 - R05
4 Design Page 75 of 87
C1-Public Early production information