Datasheet

ZED-F9T-Data sheet
Since the maximum SCL clock frequency is 400 kHz, the maximum bit rate is 400 kbit/s. The
interface stretches the clock when slowed down while serving interrupts, therefore the real bit rates
may be slightly lower.
The I2C interface is only available with the UART default mode. If the SPI interface is
selected by using D_SEL = 0, the I2C interface is not available.
Figure 4: ZED-F9T timing module I2C slave specification
Symbol Parameter Min (Standard /
Fast mode)
Max Unit
f
SCL
SCL clock frequency 0 400 kHz
t
HD;STA
Hold time (repeated) START condition 4.0/1 - µs
t
LOW
Low period of the SCL clock 5/2 - µs
t
HIGH
High period of the SCL clock 4.0/1 - µs
t
SU;STA
Set-up time for a repeated START condition 5/1 - µs
t
HD;DAT
Data hold time 0/0 - µs
t
SU;DAT
Data set-up time 250/100 ns
t
r
Rise time of both SDA and SCL signals - 1000/300 (for C = 400pF) ns
t
f
Fall time of both SDA and SCL signals - 300/300 (for C = 400pF) ns
t
SU;STO
Set-up time for STOP condition 4.0/1 - µs
t
BUF
Bus-free time between a STOP and START
condition
5/2 - µs
t
VD;DAT
Data valid time - 4/1 µs
t
VD;ACK
Data valid acknowledge time - 4/1 µs
V
nL
Noise margin at the low level 0.1 VCC - V
V
nH
Noise margin at the high level 0.2 VCC - V
Table 16: ZED-F9T I2C slave timings and specifications
UBX-18053713 - R06
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5 Communications interfaces Page 16 of 23
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