Data Sheet

SAM-M8Q - Data Sheet

UBX-16012619 - R04 Production Information Functional description

Page 11 of 25

For time aiding, hardware time synchronization can be achieved by connecting an accurate time pulse to the

EXTINT pin.

Frequency aiding can be implemented by connecting a periodic rectangular signal with a frequency up to

500 kHz and arbitrary duty cycle to the EXTINT pin. (The low/high phase duration of the cycle must not be

shorter than 50 ns.) Provide the applied frequency value to the receiver using UBX messages.

1.14 TIMEPULSE

A configurable time pulse signal is available with all u-blox M8 modules.

The TIMEPULSE output generates pulse trains synchronized with GPS or UTC time grid with intervals

configurable over a wide frequency range. Thus it may be used as a low frequency time synchronization pulse or

as a high frequency reference signal.

By default, the time pulse signal is configured to 1 pulse per second. For more information, see the u-blox 8 /

u-blox M8 Receiver Description Including Protocol Specification [2].

1.15 Protocols and interfaces

Protocol

Type

NMEA 0183, version 4.0 (V2.1, V2.3 or V4.1

configurable)

Input/output, ASCII

UBX

Input/output, binary, u-blox proprietary

RTCM

Input message, 1, 2, 3, 9

Table 4: Available Protocols

All protocols are available on UART and DDC (I

C compliant). For specification of the various protocols, see the

u-blox 8 / u-blox M8 Receiver Description Including Protocol Specification [2].

1.16 Interfaces

A number of interfaces are provided either for data communication or memory access. The embedded firmware

uses these interfaces according to their respective protocol specifications.

1.16.1 UART

The SAM-M8Q GNSS patch antenna module includes one UART interface, which can be used for communication

to a host. It supports configurable baud rates. For supported baud rates, see the u-blox 8 / u-blox M8 Receiver

Description Including Protocol Specification [2].

Designs must allow access to the UART and the SAFEBOOT_N function pin for future service, updates

and reconfiguration.

1.16.2 Display Data Channel (DDC)

An I

C compliant DDC interface is available for communication with an external host CPU or with u-blox cellular

modules. The interface can be operated in slave mode only. The DDC protocol and electrical interface are fully

compatible with Fast-Mode of the I

C industry standard. Since the maximum SCL clock frequency is 400 kHz, the

maximum transfer rate is 400 kb/s.

The maximum bit rate is 400 kb/s. The interface stretches the clock when slowed down when serving

interrupts, so real bit rates may be slightly lower.