User Manual

ZED-F9P-Data Sheet
UBX-17051259 - R02

5 Communications
interfaces
Page 16 of 24
Advance Information
is 400 kHz, the maximum bit rate is 400 kbit/s. The interface stretches the clock when slowed down
while serving interrupts, therefore the real bit rates may be slightly lower.
The I2C interface is only available with the UART default mode. If the SPI interface is selected
by using D_SEL = 0, the I2C interface is not available.
Figure 5: ZED-F9P high precision receiver I2C slave specification
Symbol Parameter Min Max Unit
VlL LOW-level input voltage VSS-0.3 0.3VCC V
VlH HIGH-level input voltage 0.7VCC VCC+0.3 V
VOL LOW-level output voltage 0.4 V
VOH HIGH-level output voltage VCC-0.4 V
fSCL SCL clock frequency 0 400 kHz
tHD;STA Hold time (repeated) START condition 4.0/1 - µs
tLOW LOW period of the SCL clock 5/2 - µs
tHIGH HIGH period of the SCL clock 4.0/1 - µs
tSU;STA Set-up time for a repeated START condition 5/1 - µs
tHD;DAT Data hold time 0/0 - µs
tSU;DAT Data set-up time 250/100 µs
tr Rise time of both SDA and SCL signals - 1000/300 (for C 400pF) µs
tf Fall time of both SDA and SCL signals - 300/300 (for C 400pF) µs
tSU;STO Set-up time for STOP condition 4.0/1 - µs
tBUF Bus free time between a STOP and START
condition
5/2 - µs
tVD;DAT Data valid time - 4/1 µs
tVD;ACK Data valid acknowledge time - 4/1 µs
VnL Noise margin at the LOW level 0.1VCC/0.1VCC - V