User Manual

ZED-F9P-Data Sheet
UBX-17051259 - R02

5 Communications
interfaces
Page 14 of 24
Advance Information
5 Communications interfaces
There are several communications interfaces including UART, SPI and I2C.
5.1 UART interface
There are two UART interfaces: UART1 and UART2. UART1 is the primary host communications
interface while UART2 is dedicated for RTCM3 corrections and NMEA. No UBX protocol is
supported. UART1 and UART2 operate up to and including a speed of 921600 baud. No hardware
flow control on UART1 and UART2 is supported.
UART1 is enabled by default if D_SEL = 1 or open.
Figure 3: ZED-F9P high precision receiver UART timing specifications
Symbol Parameter Min Max Unit
VlL LOW-level input voltage 0 0.2VCC V
VlH HIGH-level input voltage 0.7VCC VCC+0.3 V
tECH HIGH period of External data input 0 0.4 µs
tECL Low period of External data input µs
Ru Baudrate 9600 921600 bps
tCR Rise time of Data 5 ns
tCF Fall time of Data 5 ns
Table 12: ZED-F9P UART timings and specifications
5.2 SPI interface
All the inputs have internal pull-up resistors in normal operation and can be left open if not used.
All the PIOs are supplied by VCC, therefore all the voltage levels of the PIO pins are related to VCC
supply voltage
The ZED-F9P high precision receiver has a SPI slave interface that can be selected by setting D_SEL
= 0. The SPI slave interface is shared with UART1. The SPI pins available are: SPI_MISO (TXD),
SPI_MOSI (RXD), SPI_CS_N, SPI_CLK. The SPI interface is designed to allow communication to a
host CPU. The interface can be operated in slave mode only. Note that SPI is not available in the
default configuration, because its pins are shared with the UART and DDC interfaces. The maximum
transfer rate using SPI is 125 kB/s and the maximum SPI clock frequency is 5.5 MHz.
This section provides SPI timing values for the ZED-F9P high precision receiver slave operation.
Provided values A, B, C, D and E presented visually in Figure 4 and exact values with defined load
capacitance in Table 13, Table 14 and Table 15. Default SPI configuration at u-blox is CPOL = 0 and
CPHA = 0.