Data Sheet

4.9 Ethernet MAC Interface 4 PERIPHERAL INTERFACE
4.9 Ethernet MAC Interface
An IEEE-802.3-2008-compliant Media Access Controller (MAC) is provided for Ethernet LAN communications.
ESP32 requires an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber,
etc.). The PHY is connected to ESP32 through 17 signals of MII or 9 signals of RMII. With the Ethernet MAC
(EMAC) interface, the following features are supported:
• 10 Mbps and 100 Mbps rates
• Dedicated DMA controller allowing high-speed transfer between the dedicated SRAM and Ethernet MAC
• Tagged MAC frame (VLAN support)
• Half-duplex (CSMA/CD) and full-duplex operation
• MAC control sublayer (control frames)
• 32-bit CRC generation and removal
• Several address filtering modes for physical and multicast address (multicast and group addresses)
• 32-bit status code for each transmitted or received frame
• Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive FIFO are both 512
words (32-bit)
• Hardware PTP (precision time protocol) in accordance with IEEE 1588 2008 (PTP V2)
• 25 MHz/50 MHz clock output
4.10 SD/SDIO/MMC Host Controller
An SD/SDIO/MMC host controller is available on ESP32 which supports the following features:
• Secure Digital memory (SD mem Version 3.0 and Version 3.01)
• Secure Digital I/O (SDIO Version 3.0)
• Consumer Electronics Advanced Transport Architecture (CE-ATA Version 1.1)
• Multimedia Cards (MMC Version 4.41, eMMC Version 4.5 and Version 4.51)
The controller allows clock output at up to 80 MHz and in three different data-bus modes: 1-bit, 4-bit and 8-bit. It
supports two SD/SDIO/MMC4.41 cards in 4-bit data-bus mode. It also supports one SD card operating at 1.8 V
level.
4.11 Universal Asynchronous Receiver Transmitter (UART)
ESP32 has three UART interfaces, i.e. UART0, UART1 and UART2, which provide asynchronous communication
(RS232 and RS485) and IrDA support, and communicate at up to 5 Mbps. UART provides hardware management
of the CTS and RTS signals and software flow control (XON and XOFF). All of the interfaces can be accessed by
the DMA controller or directly by CPU.
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