Data Sheet

3.2 Timers and Watchdogs 3 FUNCTIONAL DESCRIPTION
3.2 Timers and Watchdogs
3.2.1 64-bit Timers
There are four general-purpose timers embedded in the ESP32. They are all 64-bit generic timers which are based
on 16-bit prescalers and 64-bit auto-reload-capable up/downcounters.
The timers feature:
• A 16-bit clock prescaler, from 2 to 65536
• A 64-bit time-base counter
• Configurable up/down time-base counter: incrementing or decrmenting
• Halt and resume of time-base counter
• Auto-reload at alarming
• Software-controlled instant reload
• Level and edge interrupt generation
3.2.2 Watchdog Timers
The ESP32 has three watchdog timers: one in each of the two timer modules (called the Main Watchdog Timer,
or MWDT) and one in the RTC module (called the RTC Watchdog Timer, or RWDT). These watchdog timers are
intended to recover from an unforeseen fault, causing the application program to abandon its normal sequence. A
watchdog timer has 4 stages. Each stage may take one of three or four actions on expiry of a programmed time
period for this stage unless the watchdog is fed or disabled. The actions are: interrupt, CPU reset, and core reset,
and system reset. Only the RWDT can trigger the system reset, and is able to reset the entire chip, including the
RTC itself. A timeout value can be set for each stage individually.
During Flash boot the RWDT and the first MWDT start automatically in order to detect and recover from booting
problems.
The ESP32 watchdogs have the following features:
• 4 stages, each can be configured or disabled separately
• Programmable time period for each stage
• One of 3 or 4 possible actions (interrupt, CPU reset, core reset, and system reset) on expiration of each stage
• 32-bit expiry counter
• Write protection, to prevent the RWDT and MWDT configuration from being inadvertently altered
• SPI Flash boot protection
If the boot process from an SPI Flash does not complete within a predetermined time period, the watchdog
will reboot the entire system.
3.3 System Clocks
3.3.1 CPU Clock
Upon reset, an external crystal clock source (2 MHz ~ 60 MHz), is selected as the default CPU clock. The external
crystal clock source also connects to a PLL to generate a high frequency clock (typically 160 MHz).
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