Data Sheet

3.1 CPU and Memory 3 FUNCTIONAL DESCRIPTION
• Up to 8 MBytes of external Flash/SRAM are memory mapped into the CPU data space, supporting 8-bit,
16-bit and 32-bit access. Data read is supported on the Flash and SRAM. Data write is supported on the
SRAM.
3.1.4 Memory Map
The structure of address mapping is shown in Figure 3. The memory and peripherals mapping of ESP32 is shown
in Table 3.
Figure 3: Address Mapping Structure
Table 3: Memory and Peripheral Mapping
Category Target Start Address End Address Size
Embedded
Memory
Internal ROM 0 0x4000_0000 0x4005_FFFF 384 KB
Internal ROM 1 0x3FF9_0000 0x3FF9_FFFF 64 KB
Internal SRAM 0 0x4007_0000 0x4009_FFFF 192 KB
Internal SRAM 1
0x3FFE_0000 0x3FFF_FFFF
128 KB
0x400A_0000 0x400B_FFFF
Internal SRAM 2 0x3FFA_E000 0x3FFD_FFFF 200 KB
RTC FAST Memory
0x3FF8_0000 0x3FF8_1FFF
8 KB
0x400C_0000 0x400C_1FFF
RTC SLOW Memory 0x5000_0000 0x5000_1FFF 8 KB
External
Memory
External Flash
0x3F40_0000 0x3F7F_FFFF 4 MB
0x400C_2000 0x40BF_FFFF
11 MB
248 KB
External SRAM 0x3F80_0000 0x3FBF_FFFF 4 MB
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