Data Sheet

3 FUNCTIONAL DESCRIPTION
3. Functional Description
This chapter describes the functions implemented in ESP32.
3.1 CPU and Memory
3.1.1 CPU
ESP32 contains two low-power Xtensa
®
32-bit LX6 microprocessors with the following features.
• 7-stage pipeline to support the clock frequency of up to 240 MHz
• 16/24-bit Instruction Set provides high code-density
• Support Floating Point Unit
• Support DSP instructions, such as 32-bit Multiplier, 32-bit Divider, and 40-bit MAC
• Support 32 interrupt vectors from about 70 interrupt sources
The dual CPUs interface through:
• Xtensa RAM/ROM Interface for instruction and data
• Xtensa Local Memory Interface for fast peripheral register access
• Interrupt with external and internal sources
• JTAG interface for debugging
3.1.2 Internal Memory
ESP32’s internal memory includes:
• 448 KBytes ROM for booting and core functions
• 520 KBytes on-chip SRAM for data and instruction
• 8 KBytes SRAM in RTC, which is called RTC SLOW Memory and can be used for co-processor accessing
during the Deep-sleep mode
• 8 KBytes SRAM in RTC, which is called RTC FAST Memory and can be used for data storage and main CPU
during RTC Boot from the Deep-sleep mode
• 1 Kbit of EFUSE, of which 256 bits are used for the system (MAC address and chip configuration) and the
remaining 768 bits are reserved for customer applications, including Flash-Encryption and Chip-ID
3.1.3 External Flash and SRAM
ESP32 supports 4 x 16 MBytes of external QSPI Flash and SRAM with hardware encryption based on AES to
protect developer’s programs and data.
ESP32 accesses external QSPI Flash and SRAM by the high-speed caches�
• Up to 16 MBytes of external Flash are memory mapped into the CPU code space, supporting 8-bit, 16-bit
and 32-bit access. Code execution is supported.
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