Data Sheet

2.4 Strapping Pins 2 PIN DEFINITIONS
2.4 Strapping Pins
ESP32 has 6 strapping pins:
• MTDI/GPIO12: internal pull-down
• GPIO0: internal pull-up
• GPIO2: internal pull-down
• GPIO4: internal pull-down
• MTDO/GPIO15: internal pull-up
• GPIO5: internal pull-up
Software can read the value of these 6 bits from the register ”GPIO_STRAPPING”.
During the chip power-on reset, the latches of the strapping pins sample the voltage level as strapping bits of ”0”
or ”1”, and hold these bits until the chip is powered down or shut down. The strapping bits configure the device
boot mode, the operating voltage of VDD_SDIO and other system initial settings.
Each strapping pin is connected with its internal pull-up/pull-down during the chip reset. Consequently, if a strap-
ping pin is unconnected or the connected external circuit is high-impendence, the internal weak pull-up/pull-down
will determine the default input level of the strapping pins.
To change the strapping bit values, users can apply the external pull-down/pull-up resistances, or apply the host
MCU’s GPIOs to control the voltage level of these pins when powering on ESP32.
After reset, the strapping pins work as the normal functions pins.
Refer to Table 2 for detailed boot modes configuration by strapping pins.
Table 2: Strapping Pins
Voltage of Internal LDO (VDD_SDIO)
Pin Default 3.3V 1.8V
MTDI Pull-down 0 1
Booting Mode
Pin Default SPI Boot Download Boot
GPIO0 Pull-up 1 0
GPIO2 Pull-down Don’t-care 0
Debugging Log on U0TXD During Booting
Pin Default U0TXD Toggling U0TXD Silent
MTDO Pull-up 1 0
Timing of SDIO Slave
Pin Default
Falling-edge Input
Falling-edge Output
Falling-edge Input
Rising-edge Output
Rising-edge Input
Falling-edge Output
Rising-edge Input
Rising-edge Output
MTDO Pull-up 0 0 1 1
GPIO5 Pull-up 0 1 0 1
Note:
Firmware can configure register bits to change the setting of ”Voltage of Internal LDO (VDD_SDIO)” and ”Timing of SDIO
Slave” after booting.
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