Datasheet

DocID022152 Rev 8 85/202
STM32F405xx, STM32F407xx Electrical characteristics
Table 20. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator enabled) or RAM
(1)
Symbol Parameter Conditions f
HCLK
Typ Max
(2)
Unit
T
A
=
25 °C
T
A
=
85 °C
T
A
=
105 °C
I
DD
Supply current in
Run mode
External clock
(3)
, all
peripherals enabled
(4)(5)
168 MHz 87 102 109
mA
144 MHz 67 80 86
120 MHz 56 69 75
90 MHz 44 56 62
60 MHz 30 42 49
30 MHz 16 28 35
25 MHz 12 24 31
16 MHz
(6)
92028
8 MHz 5 17 24
4 MHz 3 15 22
2 MHz 2 14 21
External clock
(3)
, all
peripherals disabled
(4)(5)
168 MHz 40 54 61
144 MHz 31 43 50
120 MHz 26 38 45
90 MHz 20 32 39
60 MHz 14 26 33
30 MHz 8 20 27
25 MHz 6 18 25
16 MHz
(6)
51624
8 MHz 3 15 22
4 MHz 2 14 21
2 MHz 2 14 21
1. Code and data processing running from SRAM1 using boot pins.
2. Guaranteed by characterization, tested in production at V
DD
max and f
HCLK
max with peripherals enabled.
3. External clock is 4 MHz and PLL is on when f
HCLK
> 25 MHz.
4. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for
the analog part.
5. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
6. In this case HCLK = system clock/2.