Datasheet
Table Of Contents
- Table 1. Device summary
- 1 Introduction
- 2 Description
- Table 2. STM32F405xx and STM32F407xx: features and peripheral counts (continued)
- 2.1 Full compatibility throughout the family
- 2.2 Device overview
- 2.2.1 ARM® Cortex®-M4 core with FPU and embedded Flash and SRAM
- 2.2.2 Adaptive real-time memory accelerator (ART Accelerator™)
- 2.2.3 Memory protection unit
- 2.2.4 Embedded Flash memory
- 2.2.5 CRC (cyclic redundancy check) calculation unit
- 2.2.6 Embedded SRAM
- 2.2.7 Multi-AHB bus matrix
- 2.2.8 DMA controller (DMA)
- 2.2.9 Flexible static memory controller (FSMC)
- 2.2.10 Nested vectored interrupt controller (NVIC)
- 2.2.11 External interrupt/event controller (EXTI)
- 2.2.12 Clocks and startup
- 2.2.13 Boot modes
- 2.2.14 Power supply schemes
- 2.2.15 Power supply supervisor
- 2.2.16 Voltage regulator
- 2.2.17 Regulator ON/OFF and internal reset ON/OFF availability
- 2.2.18 Real-time clock (RTC), backup SRAM and backup registers
- 2.2.19 Low-power modes
- 2.2.20 VBAT operation
- 2.2.21 Timers and watchdogs
- 2.2.22 Inter-integrated circuit interface (I²C)
- 2.2.23 Universal synchronous/asynchronous receiver transmitters (USART)
- 2.2.24 Serial peripheral interface (SPI)
- 2.2.25 Inter-integrated sound (I2S)
- 2.2.26 Audio PLL (PLLI2S)
- 2.2.27 Secure digital input/output interface (SDIO)
- 2.2.28 Ethernet MAC interface with dedicated DMA and IEEE 1588 support
- 2.2.29 Controller area network (bxCAN)
- 2.2.30 Universal serial bus on-the-go full-speed (OTG_FS)
- 2.2.31 Universal serial bus on-the-go high-speed (OTG_HS)
- 2.2.32 Digital camera interface (DCMI)
- 2.2.33 Random number generator (RNG)
- 2.2.34 General-purpose input/outputs (GPIOs)
- 2.2.35 Analog-to-digital converters (ADCs)
- 2.2.36 Temperature sensor
- 2.2.37 Digital-to-analog converter (DAC)
- 2.2.38 Serial wire JTAG debug port (SWJ-DP)
- 2.2.39 Embedded Trace Macrocell™
- 3 Pinouts and pin description
- 4 Memory mapping
- 5 Electrical characteristics
- 5.1 Parameter conditions
- 5.2 Absolute maximum ratings
- 5.3 Operating conditions
- 5.3.1 General operating conditions
- 5.3.2 VCAP_1/VCAP_2 external capacitor
- 5.3.3 Operating conditions at power-up / power-down (regulator ON)
- 5.3.4 Operating conditions at power-up / power-down (regulator OFF)
- 5.3.5 Embedded reset and power control block characteristics
- 5.3.6 Supply current characteristics
- Table 20. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM
- Table 21. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled)
- Table 22. Typical and maximum current consumption in Sleep mode
- Table 23. Typical and maximum current consumptions in Stop mode
- Table 24. Typical and maximum current consumptions in Standby mode
- Table 25. Typical and maximum current consumptions in VBAT mode
- Table 26. Typical current consumption in Run mode, code with data processing running from Flash memory, regulator ON (ART accelerator enabled except prefetch), VDD = 1.8 V
- Table 27. Switching output I/O current consumption
- Table 28. Peripheral current consumption
- 5.3.7 Wakeup time from low-power mode
- 5.3.8 External clock source characteristics
- 5.3.9 Internal clock source characteristics
- 5.3.10 PLL characteristics
- 5.3.11 PLL spread spectrum clock generation (SSCG) characteristics
- 5.3.12 Memory characteristics
- 5.3.13 EMC characteristics
- 5.3.14 Absolute maximum ratings (electrical sensitivity)
- 5.3.15 I/O current injection characteristics
- 5.3.16 I/O port characteristics
- 5.3.17 NRST pin characteristics
- 5.3.18 TIM timer characteristics
- 5.3.19 Communications interfaces
- Table 54. I2C analog filter characteristics
- Table 55. SPI dynamic characteristics
- Table 56. I2S dynamic characteristics
- Table 57. USB OTG FS startup time
- Table 58. USB OTG FS DC electrical characteristics
- Table 59. USB OTG FS electrical characteristics
- Table 60. USB HS DC electrical characteristics
- Table 61. USB HS clock timing parameters
- Table 62. ULPI timing
- Table 63. Ethernet DC electrical characteristics
- Table 64. Dynamic characteristics: Eternity MAC signals for SMI
- Table 65. Dynamic characteristics: Ethernet MAC signals for RMII
- Table 66. Dynamic characteristics: Ethernet MAC signals for MII
- 5.3.20 CAN (controller area network) interface
- 5.3.21 12-bit ADC characteristics
- 5.3.22 Temperature sensor characteristics
- 5.3.23 VBAT monitoring characteristics
- 5.3.24 Embedded reference voltage
- 5.3.25 DAC electrical characteristics
- 5.3.26 FSMC characteristics
- Table 75. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings
- Table 76. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
- Table 77. Asynchronous multiplexed PSRAM/NOR read timings
- Table 78. Asynchronous multiplexed PSRAM/NOR write timings
- Table 79. Synchronous multiplexed NOR/PSRAM read timings
- Table 80. Synchronous multiplexed PSRAM write timings
- Table 81. Synchronous non-multiplexed NOR/PSRAM read timings
- Table 82. Synchronous non-multiplexed PSRAM write timings
- Table 83. Switching characteristics for PC Card/CF read and write cycles in attribute/common space
- Table 84. Switching characteristics for PC Card/CF read and write cycles in I/O space
- Table 85. Switching characteristics for NAND Flash read cycles
- Table 86. Switching characteristics for NAND Flash write cycles
- 5.3.27 Camera interface (DCMI) timing specifications
- 5.3.28 SD/SDIO MMC card host interface (SDIO) characteristics
- 5.3.29 RTC characteristics
- 6 Package information
- 7 Part numbering
- Appendix A Application block diagrams
- 8 Revision history
Pinouts and pin description STM32F405xx, STM32F407xx
54/202 DocID022152 Rev 8
- - 60 82 M15 101 PD13 I/O FT -
FSMC_A18/TIM4_CH2/
EVENTOUT
-
- - - 83 - 102 V
SS
S- - -
- - - 84 J13 103 V
DD
S- - -
- F2 61 85 M14 104 PD14 I/O FT -
FSMC_D0/TIM4_CH3/
EVENTOUT/ EVENTOUT
-
- F1 62 86 L14 105 PD15 I/O FT -
FSMC_D1/TIM4_CH4/
EVENTOUT
-
- - - 87 L15 106 PG2 I/O FT - FSMC_A12/ EVENTOUT -
- - - 88 K15 107 PG3 I/O FT - FSMC_A13/ EVENTOUT -
- - - 89 K14 108 PG4 I/O FT - FSMC_A14/ EVENTOUT -
- - - 90 K13 109 PG5 I/O FT - FSMC_A15/ EVENTOUT -
- - - 91 J15 110 PG6 I/O FT - FSMC_INT2/ EVENTOUT -
- - - 92 J14 111 PG7 I/O FT -
FSMC_INT3 /USART6_CK/
EVENTOUT
-
- - - 93 H14 112 PG8 I/O FT -
USART6_RTS /
ETH_PPS_OUT/
EVENTOUT
-
---94G12113 V
SS
S- - -
---95H13114 V
DD
S- - -
37 F3 63 96 H15 115 PC6 I/O FT -
I2S2_MCK /
TIM8_CH1/SDIO_D6 /
USART6_TX /
DCMI_D0/TIM3_CH1/
EVENTOUT
-
38 E1 64 97 G15 116 PC7 I/O FT -
I2S3_MCK /
TIM8_CH2/SDIO_D7 /
USART6_RX /
DCMI_D1/TIM3_CH2/
EVENTOUT
-
39 E2 65 98 G14 117 PC8 I/O FT -
TIM8_CH3/SDIO_D0
/TIM3_CH3/ USART6_CK /
DCMI_D2/ EVENTOUT
-
Table 7. STM32F40xxx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)
(1)
Pin type
I / O structure
Notes
Alternate functions
Additional
functions
LQFP64
WLCSP90
LQFP100
LQFP144
UFBGA176
LQFP176