Datasheet

DocID022152 Rev 8 201/202
STM32F405xx, STM32F407xx Revision history
22-Oct-2015 6
In the whole document, updated notes related to values guaranteed by
design or by characterization.
Updated Table 34: HSI oscillator characteristics.
Changed f
VCO_OUT
minimum value and VCO freq to 100 MHz in
Table 36: Main PLL characteristics and Table 37: PLLI2S (audio PLL)
characteristics.
Updated Figure 39: SPI timing diagram - slave mode and CPHA = 0.
Updated Figure 53: 12-bit buffered /non-buffered DAC.
Removed note 1 related to better performance using a restricted V
DD
range in Table 68: ADC accuracy at fADC = 30 MHz.
Upated Figure 84: LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat
package outline.
Updated Figure 87: UFBGA176+25 ball, 10 x 10 mm, 0.65 mm pitch,
ultra fine pitch ball grid array package outline and Table 95:
UFBGA176+25 ball, 10 × 10 × 0.65 mm pitch, ultra thin fine pitch ball
grid array mechanical data.
16-Mar-2016 7
Updated Figure 2: Compatible board design
STM32F10xx/STM32F2/STM32F40xxx for LQFP100 package.
Updated |V
SSX− VSS| in Table 11: Voltage characteristics to add V
REF
−
.
Added V
REF
−
in Table 67: ADC characteristics.
Updated Table 90: WLCSP90 - 4.223 x 3.969 mm, 0.400 mm pitch
wafer level chip scale package mechanical data.
09-Sep-2016 8
Remove note 1 below Figure 5: STM32F40xxx block diagram.
Updated definition of stresses above maximum ratings in Section 5.2:
Absolute maximum ratings.
Updated t
h(NSS
) in Figure 39: SPI timing diagram - slave mode and
CPHA = 0Figure and Figure 40: SPI timing diagram - slave mode and
CPHA = 1.
Added note related to optional marking and inset/upset marks in all
package marking sections.
Updated Figure 87: UFBGA176+25 ball, 10 x 10 mm, 0.65 mm pitch,
ultra fine pitch ball grid array package outline and Table 95:
UFBGA176+25 ball, 10 × 10 × 0.65 mm pitch, ultra thin fine pitch ball
grid array mechanical data.
Table 100. Document revision history (continued)
Date Revision Changes