Datasheet

Electrical characteristics STM32F405xx, STM32F407xx
148/202 DocID022152 Rev 8
Table 79. Synchronous multiplexed NOR/PSRAM read timings
(1)(2)
1. C
L
= 30 pF.
2. Guaranteed by characterization.
Symbol Parameter Min Max Unit
t
w(CLK)
FSMC_CLK period 2T
HCLK
-ns
t
d(CLKL-NExL)
FSMC_CLK low to FSMC_NEx low (x=0..2) - 0 ns
t
d(CLKL-NExH)
FSMC_CLK low to FSMC_NEx high (x= 0…2) 2 - ns
t
d(CLKL-NADVL)
FSMC_CLK low to FSMC_NADV low - 2 ns
t
d(CLKL-NADVH)
FSMC_CLK low to FSMC_NADV high 2 - ns
t
d(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns
t
d(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x=16…25) 0 - ns
t
d(CLKL-NOEL)
FSMC_CLK low to FSMC_NOE low - 0 ns
t
d(CLKL-NOEH)
FSMC_CLK low to FSMC_NOE high 2 - ns
t
d(CLKL-ADV)
FSMC_CLK low to FSMC_AD[15:0] valid - 4.5 ns
t
d(CLKL-ADIV)
FSMC_CLK low to FSMC_AD[15:0] invalid 0 - ns
t
su(ADV-CLKH)
FSMC_A/D[15:0] valid data before FSMC_CLK high 6 - ns
t
h(CLKH-ADV)
FSMC_A/D[15:0] valid data after FSMC_CLK high 0 - ns
t
su(NWAIT-CLKH)
FSMC_NWAIT valid before FSMC_CLK high 4 - ns
t
h(CLKH-NWAIT)
FSMC_NWAIT valid after FSMC_CLK high 0 - ns