Datasheet

Electrical characteristics STM32F405xx, STM32F407xx
130/202 DocID022152 Rev 8
Figure 45. ULPI timing diagram
Frequency (steady state) ±500 ppm F
STEADY
59.97 60 60.03 MHz
Duty cycle (first transition) 8-bit ±10% D
START_8BIT
40 50 60 %
Duty cycle (steady state) ±500 ppm D
STEADY
49.975 50 50.025 %
Time to reach the steady state frequency and
duty cycle after the first transition
T
STEADY
--1.4ms
Clock startup time after the
de-assertion of SuspendM
Peripheral T
START_DEV
--5.6
ms
Host T
START_HOST
---
PHY preparation time after the first transition
of the input clock
T
PREP
---µs
1. Guaranteed by design.
Table 62. ULPI timing
Parameter Symbol
Value
(1)
1. V
DD
= 2.7 V to 3.6 V and T
A
= –40 to 85 °C.
Unit
Min. Max.
Control in (ULPI_DIR) setup time
t
SC
-2.0
ns
Control in (ULPI_NXT) setup time - 1.5
Control in (ULPI_DIR, ULPI_NXT) hold time t
HC
0-
Data in setup time t
SD
-2.0
Data in hold time t
HD
0-
Control out (ULPI_STP) setup time and hold time t
DC
-9.2
Data out available from clock rising edge t
DD
-10.7
Table 61. USB HS clock timing parameters
(1)
Parameter Symbol Min Nominal Max Unit
#LOCK
#ONTROL)N
5,0)?$)2
5,0)?.84
DATA)N
BIT
#ONTROLOUT
5,0)?340
DATAOUT
BIT
T
$$
T
$#
T
($
T
3$
T
(#
T
3#
AIC
T
$#