Datasheet

DocID022152 Rev 8 115/202
STM32F405xx, STM32F407xx Electrical characteristics
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters.
V
HYS
FT, TTa and NRST I/O input
hysteresis
1.7 V
≤ V
DD
≤ 3.6 V 10%V
DD
(3)
--
V
BOOT0 I/O input hysteresis
1.75 V
≤ V
DD
≤ 3.6 V
-40 °C
≤ T
A
≤ 105 °C
0.1 - -
1.7 V
≤ V
DD
≤ 3.6 V
0 °C
≤ T
A
≤ 105 °C
I
lkg
I/O input leakage current
(4)
V
SS
≤ V
IN
≤ V
DD
--±1
µA
I/O FT input leakage current
(5)
V
IN
= 5 V - - 3
R
PU
Weak pull-up
equivalent
resistor
(6)
All pins
except for
PA10 and
PB12
(OTG_FS_ID,
OTG_HS_ID)
V
IN
= V
SS
30 40 50
kΩ
PA10 and
PB12
(OTG_FS_ID,
OTG_HS_ID)
-71014
R
PD
Weak pull-down
equivalent
resistor
(7)
All pins
except for
PA10 and
PB12
V
IN
= V
DD
30 40 50
PA10 and
PB12
-71014
C
IO
(8)
I/O pin
capacitance
-5-pF
1. Guaranteed by design.
2. Tested in production.
3. With a minimum of 200 mV.
4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 47: I/O
current injection susceptibility
5. To sustain a voltage higher than V
DD
+ 0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be
higher than the maximum value, if negative current is injected on adjacent pins. Refer to Table 47: I/O current injection
susceptibility.
6. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS. This PMOS
contribution
to the series resistance is minimum (~10% order).
7. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS
contribution
to the series resistance is minimum (~10% order).
8. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization.
Table 48. I/O static characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit