Datasheet

DocID022152 Rev 8 195/202
STM32F405xx, STM32F407xx Revision history
31-May-2012
3
(continued)
Removed f
HSE_ext
typical value in Table 30: High-speed external user
clock characteristics. Updated Table 32: HSE 4-26 MHz oscillator
characteristics and Table 33: LSE oscillator characteristics (fLSE =
32.768 kHz).
Added f
PLL48_OUT
maximum value in Table 36: Main PLL
characteristics.
Modified equation 1 and 2 in Section 5.3.11: PLL spread spectrum
clock generation (SSCG) characteristics.
Updated Table 39: Flash memory characteristics, Table 40: Flash
memory programming, and Table 41: Flash memory programming with
VPP.
Updated Section : Output driving current.
Table 56: I
2
C characteristics: Note 4 updated and applied to t
h(SDA)
in
Fast mode, and removed note 4 related to t
h(SDA)
minimum value.
Updated Table 67: ADC characteristics. Updated note concerning ADC
accuracy vs. negative injection current below Table 68: ADC accuracy
at fADC = 30 MHz.
Added WLCSP90 thermal resistance in Table 98: Package thermal
characteristics.
Updated Table 90: WLCSP90 - 4.223 x 3.969 mm, 0.400 mm pitch
wafer level chip scale package mechanical data.
Updated Figure 87: UFBGA176+25 ball, 10 x 10 mm, 0.65 mm pitch,
ultra fine pitch ball grid array package outline and Table 95:
UFBGA176+25 ball, 10 × 10 × 0.65 mm pitch, ultra thin fine pitch ball
grid array mechanical data.
Added Figure 91: LQFP176 - 176-pin, 24 x 24 mm low profile quad flat
recommended footprint.
Removed 256 and 768 Kbyte Flash memory density from Table 99:
Ordering information scheme.
Table 100. Document revision history (continued)
Date Revision Changes