Datasheet
Table Of Contents
- Table 1. Device summary
- 1 Introduction
- 2 Description
- Table 2. STM32F405xx and STM32F407xx: features and peripheral counts (continued)
- 2.1 Full compatibility throughout the family
- 2.2 Device overview
- 2.2.1 ARM® Cortex®-M4 core with FPU and embedded Flash and SRAM
- 2.2.2 Adaptive real-time memory accelerator (ART Accelerator™)
- 2.2.3 Memory protection unit
- 2.2.4 Embedded Flash memory
- 2.2.5 CRC (cyclic redundancy check) calculation unit
- 2.2.6 Embedded SRAM
- 2.2.7 Multi-AHB bus matrix
- 2.2.8 DMA controller (DMA)
- 2.2.9 Flexible static memory controller (FSMC)
- 2.2.10 Nested vectored interrupt controller (NVIC)
- 2.2.11 External interrupt/event controller (EXTI)
- 2.2.12 Clocks and startup
- 2.2.13 Boot modes
- 2.2.14 Power supply schemes
- 2.2.15 Power supply supervisor
- 2.2.16 Voltage regulator
- 2.2.17 Regulator ON/OFF and internal reset ON/OFF availability
- 2.2.18 Real-time clock (RTC), backup SRAM and backup registers
- 2.2.19 Low-power modes
- 2.2.20 VBAT operation
- 2.2.21 Timers and watchdogs
- 2.2.22 Inter-integrated circuit interface (I²C)
- 2.2.23 Universal synchronous/asynchronous receiver transmitters (USART)
- 2.2.24 Serial peripheral interface (SPI)
- 2.2.25 Inter-integrated sound (I2S)
- 2.2.26 Audio PLL (PLLI2S)
- 2.2.27 Secure digital input/output interface (SDIO)
- 2.2.28 Ethernet MAC interface with dedicated DMA and IEEE 1588 support
- 2.2.29 Controller area network (bxCAN)
- 2.2.30 Universal serial bus on-the-go full-speed (OTG_FS)
- 2.2.31 Universal serial bus on-the-go high-speed (OTG_HS)
- 2.2.32 Digital camera interface (DCMI)
- 2.2.33 Random number generator (RNG)
- 2.2.34 General-purpose input/outputs (GPIOs)
- 2.2.35 Analog-to-digital converters (ADCs)
- 2.2.36 Temperature sensor
- 2.2.37 Digital-to-analog converter (DAC)
- 2.2.38 Serial wire JTAG debug port (SWJ-DP)
- 2.2.39 Embedded Trace Macrocell™
- 3 Pinouts and pin description
- 4 Memory mapping
- 5 Electrical characteristics
- 5.1 Parameter conditions
- 5.2 Absolute maximum ratings
- 5.3 Operating conditions
- 5.3.1 General operating conditions
- 5.3.2 VCAP_1/VCAP_2 external capacitor
- 5.3.3 Operating conditions at power-up / power-down (regulator ON)
- 5.3.4 Operating conditions at power-up / power-down (regulator OFF)
- 5.3.5 Embedded reset and power control block characteristics
- 5.3.6 Supply current characteristics
- Table 20. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM
- Table 21. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled)
- Table 22. Typical and maximum current consumption in Sleep mode
- Table 23. Typical and maximum current consumptions in Stop mode
- Table 24. Typical and maximum current consumptions in Standby mode
- Table 25. Typical and maximum current consumptions in VBAT mode
- Table 26. Typical current consumption in Run mode, code with data processing running from Flash memory, regulator ON (ART accelerator enabled except prefetch), VDD = 1.8 V
- Table 27. Switching output I/O current consumption
- Table 28. Peripheral current consumption
- 5.3.7 Wakeup time from low-power mode
- 5.3.8 External clock source characteristics
- 5.3.9 Internal clock source characteristics
- 5.3.10 PLL characteristics
- 5.3.11 PLL spread spectrum clock generation (SSCG) characteristics
- 5.3.12 Memory characteristics
- 5.3.13 EMC characteristics
- 5.3.14 Absolute maximum ratings (electrical sensitivity)
- 5.3.15 I/O current injection characteristics
- 5.3.16 I/O port characteristics
- 5.3.17 NRST pin characteristics
- 5.3.18 TIM timer characteristics
- 5.3.19 Communications interfaces
- Table 54. I2C analog filter characteristics
- Table 55. SPI dynamic characteristics
- Table 56. I2S dynamic characteristics
- Table 57. USB OTG FS startup time
- Table 58. USB OTG FS DC electrical characteristics
- Table 59. USB OTG FS electrical characteristics
- Table 60. USB HS DC electrical characteristics
- Table 61. USB HS clock timing parameters
- Table 62. ULPI timing
- Table 63. Ethernet DC electrical characteristics
- Table 64. Dynamic characteristics: Eternity MAC signals for SMI
- Table 65. Dynamic characteristics: Ethernet MAC signals for RMII
- Table 66. Dynamic characteristics: Ethernet MAC signals for MII
- 5.3.20 CAN (controller area network) interface
- 5.3.21 12-bit ADC characteristics
- 5.3.22 Temperature sensor characteristics
- 5.3.23 VBAT monitoring characteristics
- 5.3.24 Embedded reference voltage
- 5.3.25 DAC electrical characteristics
- 5.3.26 FSMC characteristics
- Table 75. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings
- Table 76. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
- Table 77. Asynchronous multiplexed PSRAM/NOR read timings
- Table 78. Asynchronous multiplexed PSRAM/NOR write timings
- Table 79. Synchronous multiplexed NOR/PSRAM read timings
- Table 80. Synchronous multiplexed PSRAM write timings
- Table 81. Synchronous non-multiplexed NOR/PSRAM read timings
- Table 82. Synchronous non-multiplexed PSRAM write timings
- Table 83. Switching characteristics for PC Card/CF read and write cycles in attribute/common space
- Table 84. Switching characteristics for PC Card/CF read and write cycles in I/O space
- Table 85. Switching characteristics for NAND Flash read cycles
- Table 86. Switching characteristics for NAND Flash write cycles
- 5.3.27 Camera interface (DCMI) timing specifications
- 5.3.28 SD/SDIO MMC card host interface (SDIO) characteristics
- 5.3.29 RTC characteristics
- 6 Package information
- 7 Part numbering
- Appendix A Application block diagrams
- 8 Revision history
DocID022152 Rev 8 191/202
STM32F405xx, STM32F407xx Revision history
8 Revision history
Table 100. Document revision history
Date Revision Changes
15-Sep-2011 1 Initial release.
24-Jan-2012 2
Added WLCSP90 package on cover page.
Renamed USART4 and USART5 into UART4 and UART5,
respectively.
Updated number of USB OTG HS and FS in Table 2: STM32F405xx
and STM32F407xx: features and peripheral counts.
Updated Figure 3: Compatible board design between
STM32F10xx/STM32F2/STM32F40xxx for LQFP144 package and
Figure 4: Compatible board design between STM32F2 and
STM32F40xxx for LQFP176 and BGA176 packages, and removed
note 1 and 2.
Updated Section 2.2.9: Flexible static memory controller (FSMC).
Modified I/Os used to
reprogram the Flash memory for CAN2 and
USB OTG FS in Section 2.2.13: Boot modes.
Updated note in Section 2.2.14: Power supply schemes.
PDR_ON no more available on LQFP100 package. Updated
Section 2.2.16: Voltage regulator. Updated condition to obtain a
minimum supply voltage of 1.7 V in the whole document.
Renamed USART4/5 to UART4/5 and added LIN and IrDA feature for
UART4 and UART5 in Table 5: USART feature comparison.
Removed support of I2C for OTG PHY in Section 2.2.30: Universal
serial bus on-the-go full-speed (OTG_FS).
Added Table 6: Legend/abbreviations used in the pinout table.
Table 7: STM32F40xxx pin and ball definitions: replaced V
SS
_3,
V
SS
_4, and V
SS
_8 by V
SS
; reformatted Table 7: STM32F40xxx pin and
ball definitions to better highlight I/O structure, and alternate functions
versus additional functions; signal corresponding to LQFP100 pin 99
changed from PDR_ON to V
SS
; EVENTOUT added in the list of
alternate functions for all I/Os; ADC3_IN8 added as alternate function
for PF10; FSMC_CLE and FSMC_ALE added as alternate functions
for PD11 and PD12, respectively; PH10 alternate function
TIM15_CH1_ETR renamed TIM5_CH1; updated PA4 and PA5 I/O
structure to TTa.
Removed OTG_HS_SCL, OTG_HS_SDA, OTG_FS_INTN in Table 7:
STM32F40xxx pin and ball definitions and Table 9: Alternate function
mapping.
Changed TCM data RAM to CCM data RAM in Figure 18:
STM32F40xxx memory map.
Added I
VDD
and I
VSS
maximum values in Table 12: Current
characteristics.
Added Note 1 related to f
HCLK
, updated Note 2 in Table 14: General
operating conditions, and added maximum power dissipation values.
Updated Table 15: Limitations depending on the operating power
supply range.