Datasheet

DocID022152 Rev 8 161/202
STM32F405xx, STM32F407xx Electrical characteristics
5.3.27 Camera interface (DCMI) timing specifications
Unless otherwise specified, the parameters given in Table 87 for DCMI are derived from
tests performed under the ambient temperature, f
HCLK
frequency and V
DD
supply voltage
summarized in
Table 13, with the following configuration:
• PCK polarity: falling
• VSYNC and HSYNC polarity: high
• Data format: 14 bits
Figure 72. DCMI timing diagram
Table 86. Switching characteristics for NAND Flash write cycles
(1)
1. C
L
= 30 pF.
Symbol Parameter Min Max Unit
t
w(NWE)
FSMC_NWE low width 4T
HCLK
–1 4T
HCLK
+ 3 ns
t
v(NWE-D)
FSMC_NWE low to FSMC_D[15-0] valid - 0 ns
t
h(NWE-D)
FSMC_NWE high to FSMC_D[15-0] invalid 3T
HCLK
–2 - ns
t
d(D-NWE)
FSMC_D[15-0] valid before FSMC_NWE high 5T
HCLK
–3 - ns
t
d(ALE-NWE)
FSMC_ALE valid before FSMC_NWE low - 3T
HCLK
ns
t
h(NWE-ALE)
FSMC_NWE high to FSMC_ALE invalid 3T
HCLK
–2 - ns
Table 87. DCMI characteristics
(1)
Symbol ParameterMinMaxUnit
Frequency ratio DCMI_PIXCLK/f
HCLK
-0.4
DCMI_PIXCLK Pixel clock input - 54 MHz
D
pixel
Pixel clock input duty cycle 30 70 %
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