Datasheet

DocID022152 Rev 8 145/202
STM32F405xx, STM32F407xx Electrical characteristics
Figure 56. Asynchronous multiplexed PSRAM/NOR read waveforms
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Table 77. Asynchronous multiplexed PSRAM/NOR read timings
(1)(2)
Symbol Parameter Min Max Unit
t
w(NE)
FSMC_NE low time 3T
HCLK
–1 3T
HCLK
+1 ns
t
v(NOE_NE)
FSMC_NEx low to FSMC_NOE low 2T
HCLK
–0.5 2T
HCLK
+0.5 ns
t
w(NOE)
FSMC_NOE low time T
HCLK
–1 T
HCLK
+1 ns
t
h(NE_NOE)
FSMC_NOE high to FSMC_NE high hold time 0 - ns
t
v(A_NE)
FSMC_NEx low to FSMC_A valid - 3 ns
t
v(NADV_NE)
FSMC_NEx low to FSMC_NADV low 1 2 ns
t
w(NADV)
FSMC_NADV low time T
HCLK
– 2 T
HCLK
+1 ns
t
h(AD_NADV)
FSMC_AD(adress) valid hold time after FSMC_NADV high) T
HCLK
-ns
t
h(A_NOE)
Address hold time after FSMC_NOE high T
HCLK
–1 - ns
t
h(BL_NOE)
FSMC_BL time after FSMC_NOE high 0 - ns
t
v(BL_NE)
FSMC_NEx low to FSMC_BL valid - 2 ns
t
su(Data_NE)
Data to FSMC_NEx high setup time T
HCLK
+4 - ns
t
su(Data_NOE)
Data to FSMC_NOE high setup time T
HCLK
+4 - ns
t
h(Data_NE)
Data hold time after FSMC_NEx high 0 - ns
t
h(Data_NOE)
Data hold time after FSMC_NOE high 0 - ns
1. C
L
= 30 pF.
2. Guaranteed by characterization.