Datasheet

DocID022152 Rev 8 121/202
STM32F405xx, STM32F407xx Electrical characteristics
5.3.19 Communications interfaces
I
2
C interface characteristics
The I
2
C interface meets the timings requirements of the I
2
C-bus specification and user
manual rev. 03 for:
• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s.
The I
2
C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to RM0090 reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and V
DD
is disabled, but is still present. Refer to
Section 5.3.16: I/O port characteristics
for more details on the I
2
C I/O characteristics
.
All I
2
C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog
filter characteristics:
Table 53. Characteristics of TIMx connected to the APB2 domain
(1)
1. TIMx is used as a general term to refer to the TIM1, TIM8, TIM9, TIM10, and TIM11 timers.
Symbol Parameter Conditions Min Max Unit
t
res(TIM)
Timer resolution time
AHB/APB2
prescaler distinct
from 1, f
TIMxCLK
=
168 MHz
1-t
TIMxCLK
5.95 - ns
AHB/APB2
prescaler = 1,
f
TIMxCLK
= 84 MHz
1-t
TIMxCLK
11.9 - ns
f
EXT
Timer external clock
frequency on CH1 to
CH4
f
TIMxCLK
=
168 MHz
APB2 = 84 MHz
0f
TIMxCLK
/2 MHz
084MHz
Res
TIM
Timer resolution - 16 bit
t
COUNTER
16-bit counter clock
period when internal
clock is selected
1 65536 t
TIMxCLK
t
MAX_COUNT
Maximum possible count - 32768 t
TIMxCLK
Table 54. I2C analog filter characteristics
(1)
1. Guaranteed by design.
Symbol Parameter Min Max Unit
t
AF
Maximum pulse width of spikes
that are suppressed by the analog
filter
50
(2)
2. Spikes with widths below t
AF(min)
are filtered.
260
(3)
3. Spikes with widths above t
AF(max)
are not filtered
ns