Datasheet

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STM32F405xx, STM32F407xx Electrical characteristics
5.3.17 NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R
PU
(see Table 48).
Unless otherwise specified, the parameters given in Table 51 are derived from tests
performed under the ambient temperature and V
DD
supply voltage conditions summarized
in
Table 14.
Figure 38. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the V
IL(NRST)
max level specified in
Table 51. Otherwise the reset is not taken into account by the device.
Table 51. NRST pin characteristics
Symbol Parameter Conditions Min Typ Max Unit
V
IL(NRST)
(1)
1. Guaranteed by design.
NRST Input low level voltage TTL ports
2.7 V ≤ V
DD
≤
3.6 V
--0.8
V
V
IH(NRST)
(1)
NRST Input high level voltage 2 - -
V
IL(NRST)
(1)
NRST Input low level voltage CMOS ports
1.8 V ≤ V
DD
≤
3.6 V
--0.3V
DD
V
IH(NRST)
(1)
NRST Input high level voltage 0.7V
DD
--
V
hys(NRST)
NRST Schmitt trigger voltage
hysteresis
--200-mV
R
PU
Weak pull-up equivalent resistor
(2)
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance must be minimum
(~10% order).
V
IN
= V
SS
30 40 50 kΩ
V
F(NRST)
(1)
NRST Input filtered pulse - - 100 ns
V
NF(NRST)
(1)
NRST Input not filtered pulse V
DD
> 2.7 V 300 - - ns
T
NRST_OUT
Generated reset pulse duration
Internal
Reset source
20 - - µs
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