Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129

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• Compensation every 128 Seconds – Increase or Decrease 1

• Compensation every 256 Seconds – Increase or Decrease 1

• Compensation every 512 Seconds – Increase or Decrease 1

• Compensation every 1024 Seconds – Increase or Decrease 1

• Compensation every 2048 Seconds – Increase or Decrease 1

• Compensation every 4096 Seconds – Increase or Decrease 1

• Compensation every 8192 Seconds – Increase or Decrease 1

•

Compensation every 16384 Seconds – Increase or Decrease 1

Figure 56: 1 ms Count and 1 ms Counter Relationship

2 1 0 3 2 1 0 4 3 2 1 0 3 2 1 0

0 1 2 3

+0 +0 +1 +0

1 ms

CNT

CLK

Event

1 ms

Event

ms Count

Compensation

for 1 ms CNT

9.5.3. Timeout Event Counter

The timeout event counter counts the 1ms events and the time out period (from 1 ms to 255 ms) based on the configured

value.

9.5.4. 30-Bit Counter

The 30-bit counter timer counts the 1ms event (in 1 ms resolution) and allows the software to read/write the timer value

through Registers space.

9.5.5. Time Stamp Counters

There are eight time stamps. Each time stamp has 16-bits and the corresponding interrupt source that could be individual

mask out. If the interrupt triggers, the lower 16 bits of the 24 bits of the timer loads with the corresponding time stamp.

9.5.6. PMU and FFE Wakeup

This timer allows the PMU to power up the sensor processing subsystem FFE. Once the FFE power domain is ON, a kick-

off event is sent to the FFE. There are register controls that control the timing relationship between the time that FFE is

powered up and the kick-off event is sent to the FFE, which provides for some timing flexibility for the software.