Datasheet
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129
© 2020 QuickLogic Corporation
www.quicklogic.com 92
Figure 55: Timer Block Diagram
INT x8
x8
INT Mask x8
Masked INT x8
Time Stamp x8
for FFE
Time Value
for FFE
Time Out Configuration
PMU Kick Off
FFE Kick Off
Sleep Mode
FFE Pending PD or WU
Error Configurations
32 or 16 KHz
Clock
9.5.1. 1 ms Event Counter
The 32 kHz Reference Clock 1 ms event alternates between 65 and 66 counts of clock event in the following sequence:
65
66
65
66
65
66
65 …
The 16 kHz Reference Clock 1 ms event alternates between 32 and 33 counts of clock event in the following sequence:
32
33
33
33
32
33
33
33
32
33
33 …
9.5.2. Error Correction for 1 mS Event Counter
The 1 ms event counter implementation accumulates approximately -550 µs error for every 1 second period without error
compensation occurring. As a result, an Error Correction circuit is implemented to compensate for potential errors in the
corresponding reference clock.
The following list represents multiple layer error correction compensation schemes in use:
• Compensation every 40 ms – Increase 1 or not
• Compensation every 1 Second – Increase or Decrease 1
• Compensation every 2 Second – Increase or Decrease 1
• Compensation every 4 Seconds – Increase or Decrease 1
• Compensation every 8 Seconds – Increase or Decrease 1
• Compensation every 16 Seconds – Increase or Decrease 1
• Compensation every 32 Seconds – Increase or Decrease 1
• Compensation every 64 Seconds – Increase or Decrease 1