Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129
© 2020 QuickLogic Corporation www.quicklogic.com 91
• Fully-programmable serial interface characteristics:
 Data can be 5 bits, 6 bits, 7 bits, or 8 bits
 Even, Odd, Stick, or No Parity bit generation and detection
 1 or 2 stop bit generation
 Baud rate generation, direction control up to UARTCLK/16
• IrDA SIR ENDEC block which supports:
 Programmable use of IrDA SIR or UART input/output
 IrDA SIR ENDEC functions for data rates up to 115,200 bps half-duplex
 Normal 3/16 and low-power (1.41-2.23 øs) bit durations
 Programmable division of the reference clock to generate the appropriate bit duration for low-power IrDA
modes
Timer and Counters
The EOS S3 platform supports several counters that count the clock event to generate the 1 ms event as well as time out
events for waking up the FFE and FFE power domain. Counters also provides 24-bit timers and eight time stamps for FFE,
and 30-bit timer for software use.
Clock events are generated on both edges of the reference clock. The 1 ms time out event period can be adjusted by
configuring the trim bits.
• Clock Event Generator: Generate the Clock Event base on the edge of the reference clock. The reference clock
can be either 16 kHz or 32 kHz with certain PPM error.
• 1 ms event counter: The resolution is 1 Clock Event.
• 30-bit/24-bit timer: The resolution is 1 ms (for details, see the following figure; the 30-bit timer associated with
the 1 ms event counter, the shadow 24-bit timer associated with the FFE).
• Time stamp: Eight total, timers LSB (lower 16 bits of timers) is latched once the corresponding Interrupt
triggers.
• 5 ms time-out event with less than 1% error in a two-hour period.