Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129

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Figure 54: Example Voltage Divider Circuit

ADC Input

Battery Voltage

PMOS

NMOS

ADC Measurement

Enable

The voltage divider resistors, R1 and R2 must be chosen according to the amount of voltage scaling required. It is left to

software to scale the ADC values to best determine the proper corresponding battery voltage level. In addition, the ADC

provides an enable output for the specific purpose of controlling an external voltage divider.

In this example, this enables control components M1, M2, and R3, which allow the ADC to disable the voltage divider

between ADC measurements. Not doing so results in a constant current draw on the battery. Any constant current draw

causes reduced battery life. Besides extending battery life, an additional benefit is that these components disable the

voltage divider when the EOS S3 device is in a low power state.

Universal Asynchronous Receiver Transmitter (UART)

The UART provides a serial data connection that can be used for communications and trace. The main features of UART

include:

• Programmable use as UART or IrDA SIR input/output

• Separate 32 8 transmit and 32 12 receive FIFO memory buffers to reduce CPU interrupts

• Programmable FIFO disabling for 1-byte depth

• Programmable Baud rate generator

• Standard asynchronous communication bits (start, stop and parity)

• Independent masking of transmit FIFO, receive FIFO, receive timeout, modem status, and error condition

interrupts

• Support for Direct Memory Access (DMA)

• False start bit detection

• Line break generation and detection

• Support of the modem control functions CTS and RTS

• Programmable hardware flow control