Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129
© 2020 QuickLogic Corporation www.quicklogic.com 9
Figures
Figure 1: EOS S3 Ultra Low Power multicore MCU Platform Architecture ....................................... 15
Figure 2: EOS S3 Ultra Low Power multicore MCU Platform Block Diagram................................... 19
Figure 3: Cortex M4-F Block Diagram ............................................................................................. 20
Figure 4: Recommended External Debugger Connection for ARM DS Debugger ........................... 24
Figure 5: Sensor Processing Subsystem Block Diagram ................................................................ 25
Figure 6: FFE Architecture .............................................................................................................. 26
Figure 7: Sensor Manager Architecture ........................................................................................... 28
Figure 8: I2C Modules within the EOS S3 Platform ......................................................................... 29
Figure 9: I
2
C Protocol Example ...................................................................................................... 30
Figure 10: I
2
C Block Diagram ......................................................................................................... 32
Figure 11: I
2
C Bit Command Sequences ........................................................................................ 33
Figure 12: On-Chip Programmable Logic IP Access to SPI Master for System Support .................. 34
Figure 13: SPI Interface used for Sensor Processing Subsystem Support ...................................... 36
Figure 14: SPI Slave Block Diagram ............................................................................................... 37
Figure 15: SPI Slave Protocol Diagram ........................................................................................... 39
Figure 16: SPI Slave Device ID Read Protocol ............................................................................... 39
Figure 17: SPI Master Burst Write Sequence .................................................................................. 41
Figure 18: Example Burst Read Sequence ..................................................................................... 41
Figure 19: Basic SPI Write Operation (Mode 11) ............................................................................ 42
Figure 20: Basic SPI Read Operation (Mode 11) ............................................................................ 42
Figure 21: SPI Multiple Read Operation (Mode 11) ......................................................................... 43
Figure 22: 3-Wire Basic SPI Read/Write Sequence (Mode 11) ....................................................... 43
Figure 23: muRata Command and 11-bit SPI Acceleration Data Read Sequence .......................... 43
Figure 24: AD7091 SPI Transfer Sequence .................................................................................... 44
Figure 25: SPI Block Diagram ......................................................................................................... 45
Figure 26: SPI Clock Format 0 (CPHA = 0) ..................................................................................... 46
Figure 27: SPI Clock Format 1 (CPHA = 1) ..................................................................................... 47
Figure 28: FFE AHB Master Bridge Block Diagram ......................................................................... 48
Figure 29: Voice Subsystem Block Diagram ................................................................................... 49
Figure 30: I
2
S Slave Port ................................................................................................................ 51
Figure 31: I
2
C Master AC Timing .................................................................................................... 52
Figure 32: I
2
S Timing Waveform ..................................................................................................... 53
Figure 33: PDM Microphone Timing ................................................................................................ 53
Figure 34: SPI Master AC Timing .................................................................................................... 54
Figure 35: SPI Slave Timing ........................................................................................................... 55
Figure 36: Logic Cell Block Diagram ............................................................................................... 57
Figure 37: On-Chip Programmable Logic Configurable Input/Output .............................................. 59
Figure 38: On-Chip Programmable Logic Multiplier ......................................................................... 60
Figure 39: AHB-to-Wishbone Bridge ............................................................................................... 61
Figure 40: Use Case 1: Dual Voltage Rail ....................................................................................... 65
Figure 41: Use Case 2: Single Voltage Rail .................................................................................... 66
Figure 42: Use Case 3: External Voltage Supplied ......................................................................... 66
Figure 43: Power-On Sequence of CMOS Clock ............................................................................ 67
Figure 44: Current Measurement Scheme with External Power Supplies ........................................ 69
Figure 45: Power-Down Sequence of CMOS Clock ........................................................................ 70
Figure 46: Power-On Sequence of Crystal Clock ............................................................................ 72
Figure 47: Power-Down Sequence of Crystal Clock ........................................................................ 74
Figure 48: Clock Tree ..................................................................................................................... 77