Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129

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The System DMA can perform the following tasks:

• Transfer voice data from M4-F SRAM to I

S Slave.

• Transfer data from M4-F SRAM to FFE CM (swapping).

• Transfer data from M4-F SRAM to FFE DM.

• Transfer data from FFE DM to M4-F SRAM.

• Transfer data from M4-F SRAM to on-chip programmable logic.

• Transfer data from on-chip programmable logic to M4-F SRAM.

9.2.2. SDMA Configurations

The configuration for SDMA transfers includes the following three elements:

• DMA descriptors – Each DMA channel has two associated channel descriptor structures that are normally

located in SDMA SRAM. These include the source and destination address for the channel as well as information

on number of elements to transfer, data size, transfer type, etc.

NOTE: When a channel is triggered, the DMA reads the associated descriptor from SRAM, which includes the

instructions on what actions the DMA should take. When the channel has finished completing the defined actions,

the updated descriptors are written back to the SRAM.

• DMA registers – Common configurations for the DMA, as well as DMA-generated interrupts and trigger sources

for the various channels are configured in the DMA registers. The location of the DMA descriptors in SRAM is

also configured here.

• Registers in trigger peripheral – The DMA request signals from the peripherals get generated by various events

in the peripherals; hence, it is important to configure the peripherals correctly to generate the desired DMA

requests.

Analog-to-Digital Converter

9.3.1. Overview

The ADC is an accurate, high resolution analog-to-digital converter used for voltage monitoring. To achieve excellent

repeatability and high Power Supply Rejection Ratio (PSRR), the ADC uses a 12-bit advanced fully differential delta-sigma

ADC.

The ADC is specified from T

= -40 C to +125 C and it is designed to achieve 2.0% overall accuracy.

The following figure shows a general block diagram of the ADC.

Figure 53: ADC Block Diagram

Digital Control and

Decimation Filter

MUXBattery

EOS System

1-Bit ʏʓ Modulator