Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129
© 2020 QuickLogic Corporation www.quicklogic.com 87
power. The SDMA can support a hardware/software request, and DMA requests can be from a peripheral or initiated by
software. The SDMA uses an AHB-Lite Master port for reading DMA descriptors from 128x32 bits SRAM and transferring
data from source to destination and the SDMA AHB Master port is connected to the Always-On AHB bus matrix so that
it can transfer data even when M4-F power domain is in deep sleep or shut down. The APB bus is the register interface
of the SDMA and SDMA Bridge.
Figure 52: System DMA Interface
AON AHB
Interconnect
DMAC
AHB2APB
SRAM
128x32B
AHB2SRAM
M
S
SDMA
Bridge
I2S Slave
APB-Bus-1
From I2S Slave
To M4 VIC
FPGA Interface
DMA_STALL[15:0]
DMA_ACTIVE[7:1], [11:8]
DMA_SREQ[7:1], [11:8]
DMA_REQ[7:1], [11:8]DMA_ACTIVE[15:12]
DMA_DONE[15:12]
DMA_SREQ[15:12]
DMA_REQ[15:12]
M
S
DMA_DONE[11:0]
DMA_REQ[0]
The blocks that can initiate transfer using SDMA are:
• I
2
S Slave port
• M4-F processor
• FFE
• On-chip programmable logic
System DMA supports up to 16 DMA channels. Channel assignment is listed in the following table. Each channel has a
primary and an alternate descriptor associated with it, and each description consists of four words. The descriptors are
hosted in a 128x32 bits SRAM connected to the Always-On AHB bus matrix. The SDMA bridge can generate single/burst
DMA requests to the SDMA, which is software controlled.
Table 29: SDMA Channel Assignment
Channel
Number
Primary
Channel
Programming
Alternate
Channel
Programming
Channel
Trigger
Channel
Acknowledge
Comment
0 M4-F FFE
I
2
S
M4-F Masking under software control
possible.
1-7 M4-F FFE SDMA Bridge SDMA Bridge
and M4-F
These channels are under direct
control of M4-F.
8-11 FFE M4-F SDMA Bridge SDMA Bridge
and M4-F
These channels can be controlled by
FFE or M4-F. DMA_DONE signals
associated with these channels are
connected to M4-F VIC.
12-15 M4-F FFE FPGA FPGA