Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129
© 2020 QuickLogic Corporation www.quicklogic.com 86
As with FIFO_8K, these FIFOs provide the FIFO word count on the pop side. FIFO word counts specify the exact number of
words in the FIFO regardless of packet boundaries. The AP or M4-F is expected to read the FIFO word count, and pop no
more than the count allows. In this way, the empty flag signal is never used to throttle the pop of data.
System DMA
The principal features of the SDMA include the following (illustrated in the following figure):
• Uses AHB-Lite for the DMA transfers
• Uses APB for programming the registers
• Single AHB-Lite Master for transferring data using a 32-bit address bus and 32-bit data bus
• Supports up to 16 DMA channels
• Dedicated handshake signals on each DMA channel
• Programmable priority level on each DMA channel
• Each priority level arbitrates using a fixed priority that is determined by the DMA channel number
• Supports multiple transfer types:
 Memory-to-Memory
 Memory-to-Peripheral
 Peripheral-to-Memory
• Supports multiple DMA cycle types
• Supports multiple DMA transfer data widths
• Each DMA channel can access a primary and an alternate channel control data structure
• All channel control data is stored in system memory using the little-endian format
• Performs all DMA transfers using the SINGLE AHB-Lite burst type
Figure 51: System DMA Block Diagram
AHB-Lite Master
Interface
APB Memory
Mapped Registers
Configuration Control DMA Data Transfer
Active Channel
Channel Done
Error
Requests
Stall
Mode
9.2.1. Functional Description
The SDMA aids in offloading data move tasks from the M4-F CPU and allows M4-F to sleep as long as possible to save