Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129

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The FIFO instances are listed in the following table.

Table 28: Packet FIFO Instances

Instance Depth Width Description

FIFO_8K 4096 17 Supports normal or packet FIFO modes.

Supports ring buffer mode support (16-bit data, 1-bit SOP).

Drainer logic with programmable threshold to implement ring buffer

function.

PUSH source: FFEs or M4-F.

POP destination: AP or M4-F.

FIFO_0 256 32 Supports normal FIFO modes.

PUSH source: FFEs or M4-F.

POP destination: AP or M4-F.

FIFO_1 128 32

FIFO_2 128 32

9.1.1. FIFO_8K

The FIFO_8K is a 4096x17 packet FIFO that has the following configurable options:

• Packet FIFO mode – When enabled, the FIFO behaves as a packet FIFO, otherwise, it behaves like a generic

FIFO.

• Ring buffer mode – When enabled, a small drainer block on the pop side of the FIFO will be enabled. This drainer

logic is triggered once the pop word count reaches a programmable threshold, which causes it to pop a packet

off the top of the FIFO. Once the final pop agent (AP or M4-F) is triggered by an external event to start popping

the FIFO, it will disable the drainer logic to start reading the FIFO. Care must be taken when disabling the drainer

logic to avoid any type of race condition that can cause coherency issues. One possible way of doing this is for

the AP/M4-F to disable the drainer logic before it polls the drainer logic BUSY status. The drainer is designed

only to check the enable bit at the start of the pop transactions. Controls for the muxes must consider this to

prevent going off-sync (such as changing mux control before the logic drainer is done).

NOTE: The ring buffer mode can only be used with packet FIFO mode. The software must ensure that it does not

enable the ring buffer mode for non-packet FIFO operation.

• Threshold – This register determines the FIFO threshold that triggers either the drainer logic (when used in ring

mode) or an interrupt (when used as a normal FIFO). Both threshold triggers are designed to avoid a FIFO overrun

condition.

The packet FIFO provides FIFO word count on the pop side. When used in packet FIFO mode, this indicates the exact

number of words in the FIFO that represent full packets. When used as a normal FIFO, the FIFO word count specifies the

exact number of words in the FIFO regardless of packet boundaries. The AP or M4-F is expected to read the FIFO word

count and pop no more data than allowed by the count. In this way, the empty flag signal is never used to throttle the

pop of data.

In ring buffer mode, the start of packet (SOP) signal is pushed into the FIFO as data bit[16] to alert the drainer logic and

identify the SOP on the pop side so it is able to pop packets when the threshold is reached.

9.1.2. FIFO_0, FIFO_1, FIFO_2

All three FIFOs are designed to be generic FIFOs with the following firmware configurable option:

• Threshold – This register determines the FIFO threshold that triggers an interrupt when reached. The purpose

of the threshold is to avoid a FIFO overrun condition.

• Sizes – FIFO_0 is 256x32 bits, while FIFO_1 and FIFO_2 are both 128x32 bits.