Datasheet

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9. Other Peripherals
Packet FIFO
The packet FIFO bank provides data buffering for data transfers between FFE and/or on-chip programmable logic and/or
M4-F to AP and/or M4-F. It is composed of four packet FIFOs of differing sizes. A typical use case may have the FFE push
sensor data as packets into the Packet FIFO. When a specific threshold is reached, the programmable interrupt signals to
the M4-F or AP to pop off the data for additional processing. The M4-F can also write data into the Packet FIFO and pop off
the data. The on-chip programmable logic can push data packets into the Packet FIFOs, depending on the on-chip
programmable logic configuration.
NOTE: The FFE and on-chip programmable logic cannot pop data from Packet FIFOs to perform additional processing.
Packet FIFOs are designed to support two operating modes:
• Packet mode – This FIFO mode differs from a normal FIFO in its generation of the pop side flags (empty and pop
word count). It only considers data pushed up to end-of-packet (EOP) boundaries.
• Normal FIFO mode – This mode behaves like a normal FIFO with pop side flags updated for every instance of
pushed data.
The following is a block diagram of Packet FIFO Bank (PKFB).
Figure 50: PKFB Block Diagram
Drain
256x32
ASYNCFIFO
256x32
ASYNCFIFO
512x32
ASYNCFIFO
4096x17
ASYNCFIFO
CTL
Data/CTL
DR CTL
RD Data
Data/CTL
Data/CTL
CTL
FB
ASYNCFIFO
& CTL
FFE
ASYNCFIFO
& CTL
AHB Slave
TLCI/F