Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129

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• Reset Interrupt

• FFE Message

• FFE Combined

• AP Boot

• LDOs Power Good Interrupts

• SRAM Timeout

• LPSD Voice Detect

• DMIC Voice Detect

• SDMA DONE Channel 1–11

NOTE: SDMA Channel 0 (I

S Slave) does not wake up the M4-F.

Bootstrap Modes

The EOS S3 device I/O configuration options are selected by pulling special bootstrap pins high or low, which are latched

upon de-assertion of the SYS_RSTn pin. For timing details, see the following figure.

Figure 49: Bootstrap Timing

Boot Strap Pins

SYS_RSTn

Boot Value

1 µs

(Min)

1 µs

(Min)

Do Not Care Do Not Care

The following table lists the bootstrap timing during power-on sequence.

Table 23: Bootstrap Timing During Power-On Sequence

Symbol Parameter Min. Typ. Max. Unit

BSU

Bootstrap pins setup time 1 - - µs

Bootstrap pins hold time 1 - µs

M4-F Serial Wire Debug Port Configuration

IO_19 assert high is used for Serial Wire Debug with pin IO_8, which configures I/Os used for the M4-F Serial Wire Debug.

Table 24: M4-F Serial Wire Debug Port Bootstrap Configuration

Serial Wire Debug Port Signal IO_8 Pulled Down (Default) IO_8 Pulled Up

SW_CLK IO_14 IO_45

SW_IO IO_15 IO_44