Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129
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one at the interrupt source, the other at the top-level interrupt controller.
AP: Interrupt mechanism for the AP is the same as M4, but with a different mask. All interrupt sources are
muxed to a single, combined interrupt before being sent to the AP.
8.4.2. Interrupt Sources
Interrupts sourced from each subsystem functional blocks get combined into one interrupt for each subsystem.
TOP Interrupts
Sensor/GPIO Interrupts Eight pins can be used for sensor interrupts or generic GPIO interrupts depending
on system requirements. Each interrupt can be configured to use either
edge
detection (configurable to the
positive or negative edge) or
level
detection (configurable to a high-level or a low-level setting).
M4-F Subsystem Interrupts
FPU — The Floating Point Unit (FPU) can generate interrupts on floating point events.
Bus Timeout — There are bus timeout monitors that prevent AHB/APB Slaves from locking up a system. If
there is no response after 1,024 clock cycles, an interrupt can be generated.
UART The UART can generate transmit FIFO, receive FIFO, receive timeout, modem status, and error
condition interrupts.
Timer — An interrupt can be triggered when the timer counts down to zero.
Watchdog Timer Software can enable the watchdog timer, and after counting down to 0, an interrupt
can be triggered. If the interrupt is not cleared, a reset is triggered.
SRAM An interrupt can be triggered when any segment of the 512 KB (16 instances of 32 KB) M4-F
memory is accessed when the memory is in a lower power state (e.g., in deep sleep or in shutdown mode).
FFE Interrupts
FFE Message — Eight interrupt messages can be used by FFE for various purposes.
FFE Subsystem — Sixteen interrupts are generated from the FFE subsystem, and they are combined into a
single interrupt source.
A0 Interrupts
AP Re-Boot — This interrupt is asserted when there is a need for rebooting. This occurs when all the M4-
F SRAMs are shut down for power savings, and upon wake up, rebooting is necessary.
Reset Interrupt — The SYS_RSTn pin can be used to generate an interrupt.
ADC Interrupt — Interrupt generated upon completion of analog to digital conversion.
PMU Timer This 16-bit timer (with 32 kHz clock source) can be used to wake up FFE0 from low power
mode before the FFE kickoff timer expires.
Software Interrupts — Two software interrupts can be triggered by software for handshaking between AP
and the M4-F.
LDO Power Good — Independent interrupts from LDO-2 and/or LDO-1 are triggered when the voltage falls
below the threshold value.
A1 Interrupts
Configuration DMA In wearable mode, an interrupt is asserted after the DMA download from flash to
M4-F memories is completed.
SPI Master Interrupt The configuration block can generate a combined interrupt, and this includes
interrupts from the SPI Master.
Voice Interrupts
LPSD Voice Detect — Interrupt is triggered when voice is detected by LPSD HW.
DMIC Voice Detect — Interrupt is triggered when voice is detected by DMIC.